Technology scaling has increased the transistor's susceptibility to process variations in nanometer very large scale integrated (VLSI) circuits. The effects of such variations are having a huge impact on performance and hence the timing yield of the integrated circuits. The circuit optimization objectives namely power, area, and delay are highly correlated and conflicting in nature. The inception of variations in process parameters have made their relationship intricate and more difficult to optimize. Traditional deterministic methods ignoring variation effects negatively impacts timing yield. A pessimistic worst case consideration of variations, on the other hand, can lead to severe over design. In this context, there is a strong need for re-invention of circuit optimization methods with a statistical perspective. In this dissertation, we model and develop novel variation aware solutions for circuit optimization methods such as gate sizing, timing based placement and buffer insertion. The uncertainty due to process variations is modeled using interval valued fuzzy numbers and a fuzzy programming based optimization is proposed to improve circuit yield without significant over design. In addition to the statistical optimization methods, we have proposed a novel technique that dynamically detects and creates the slack needed to accommodate the delay due to variations. The variation aware gate sizing technique is formulated as a fuzzy linear program and the uncertainty in delay due to process variations is modeled using fuzzy membership functions. The timing based placement technique, on the other hand, due to its quadratic dependence on wire length is modeled as nonlinear programming problem. The variations in timing based placement are modeled as fuzzy numbers in the fuzzy formulation and as chance constraints in the stochastic formulation. Further, we have proposed a piece-wise linear formulation for the variation aware buffer insertion and driver sizing (BIDS) problem. The BIDS problem is solved at the logic level, with look-up table based approximation of net lengths for early variation awareness.In the context of dynamic variation compensation, a delay detection circuit is used to identify the uncertainty in critical path delay. The delay detection circuit controls the instance of data capture in critical path memory flops to avoid a timing failure in the presence of variations. In summary, the various formulation and solution techniques developed in this dissertation achieve significantly better optimization compared to related works in the literature. The proposed methods have been rigorously tested on medium and large sized benchmarks to establish the validity and efficacy of the solution techniques.

Conselho Nacional de Desenvolvimento Científico e Tecnológico / This dissertation presents a methodology of capacitance estimation and power consumption in CMOS circuits combinational constituted basically of complex logic gates at logic level. The main objective in the development of this method is to provide a fast estimate of the power consumption of circuits at the logical design gates. Of this form, the considered method allows to the application of techniques to the reduction of power consumption or the alteration of the design before being prototyped. The consumed dynamic power in complex logic gates depends on the following factors: switching activity of each circuit node, voltage of supplies, parasite capacitance and clock frequency. With the exception of the parasite capacitance, all other parameters are easily determined. The analysis proposed in this dissertation, treats estimative of the dynamic power consumption of complex logic gates, through the estimate of the parasite capacitance CMOS devices. The model considered here concentrates all internal capacitances on the external gate nodes depending on the combinations of the input signals. The resulting capacitance in an only external node of an input of the gate is resulted of the transitions of inputs of the too much nodes on the node that if wants to determine. The results obtained in this work, regarding the estimate of power consumption of the complex logic gates, had been considered satisfactory, once they had presented a maximum error of 10% when compared with to the electric simulation result preformed with ELDO. Moreover, the method supplies significant reduction in the simulation time of the circuits, being able esteem the power consumption of a circuit up to 200 times faster than gotten to the simulated electric level with ELDO tool. / Este trabalho apresenta uma metodologia de estimativa de capacitâncias e de consumo de potência de circuitos CMOS constituídos basicamente por portas lógicas complexas no nível lógico. O principal objetivo no desenvolvimento deste método é fazer uma rápida previsão do consumo de potência de circuitos ainda na fase de projeto lógico composto de portas complexas. Desta forma, o método proposto permite a aplicação de técnicas de redução de consumo de potência ou a alteração de todo o projeto antes de ser prototipado. A potência dinâmica consumida em portas lógicas complexas depende dos seguintes fatores: atividade de comutação de cada nó do circuito, tensão de alimentação, freqüência de operação e da capacitância parasita. Com a exceção da capacitância parasita, todos os demais parâmetros são facilmente determinados. A análise proposta nesta dissertação, trata da aproximação (cálculo aproximado) do consumo de potência dinâmica de portas lógicas complexas, através da estimativa da capacitância parasita dos dispositivos CMOS. O modelo aqui proposto concentra as capacitâncias nos nós externos das portas, que variam em função das combinações dos sinais de entrada. A capacitância resultante, representada em um único nó externo da entrada da porta analisada, é resultado das transições dos sinais das demais entradas que agem sobre o nó que se quer determinar. Os resultados obtidos neste trabalho a respeito da estimativa de consumo potência das portas lógicas complexas foram considerados satisfatórios, pois apresentaram um erro máximo de 10% quando comparados às simulações elétricas pelo uso da ferramenta ELDO. Além disso, o método fornece significante redução no tempo de simulação dos circuitos, podendo estimar o consumo de potência de um circuito até 200 vezes mais rápido que obtido ao nível elétrico simulado com a ferramenta ELDO.