Typescript (photocopy) / vii, 190 leaves ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / Thesis (Ph.D.) Dept. of Electrical and Electronic Engineering, University of Adelaide, 1979

A program has been written for the Texas Instrument's TI-59 hand-held calculator implementing the Quine-McCluskey minimization method for logic circuit design. This program is contained on multiple magnetic cards and provides the user with the capability for combinational logic minimization of circuit design problems containing up to six variables.

A software interface between a firmware documentation system and a logic simulator named TEGAS-51 is described. The interface accepts PALASM2 inputs for PAL files. The output is an ASCII file which defines the firmware parts in TEGAS-5 format. Modules are written in FORTRAN and command routines are written in DCL on VAX 11/780 machines. No system calls are required, so portability is maintained. Limitations include the inability to load two different programs in identical firmware parts on the same design, but this can be overcome. 1GE/Calma Corporation trademark 2MMI Corporation trademark

Ho Chi Kit. / Thesis submitted in: September 2005. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (leaves 66-70). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.9 / Chapter 1.1 --- Aims and Contribution --- p.9 / Chapter 1.2 --- Dissertation Overview --- p.10 / Chapter 2 --- Literature Review --- p.11 / Chapter 2.1 --- ATPG-based Alternative Wiring --- p.11 / Chapter 2.1.1 --- Post-Layout Logic Restructuring for Performance Optimization --- p.11 / Chapter 2.1.2 --- Timing Optimization by an Improved Redundancy Addition and Removal Technique --- p.12 / Chapter 2.2 --- Logic Synthesis --- p.13 / Chapter 2.2.1 --- Local Logic Substitution Algorithm for Post-Layout Re-synthesis --- p.13 / Chapter 2.2.2 --- SIS: A System for Sequential Circuit Synthesis --- p.13 / Chapter 2.3 --- Fanout Optimization --- p.14 / Chapter 2.3.1 --- Efficient Global Fanout Optimization Algorithms --- p.14 / Chapter 2.3.2 --- Fanout Optimization under a Submicron Transistor-Level Delay Model --- p.15 / Chapter 2.4 --- Genetic Algorithm --- p.15 / Chapter 2.4.1 --- Scalability and Efficiency of Genetic Algorithms for Geometrical Applications --- p.15 / Chapter 2.4.2 --- "The Gambler's Ruin Problem, Genetic Algorithms, and the Sizing of Populations" --- p.16 / Chapter 3 --- Background --- p.18 / Chapter 3.1 --- Redundancy Addition and Removal --- p.18 / Chapter 3.2 --- REWIRE --- p.19 / Chapter 4 --- Standard Cell Logic Synthesis --- p.20 / Chapter 4.1 --- Introduction --- p.20 / Chapter 4.2 --- Objective --- p.22 / Chapter 4.3 --- Use Standard Patterns for Logic Synthesis --- p.22 / Chapter 4.4 --- Optimization --- p.25 / Chapter 4.5 --- Proposed Scheme --- p.26 / Chapter 4.6 --- Criteria for Selection of Wire --- p.28 / Chapter 4.7 --- Experimental Results --- p.30 / Chapter 4.8 --- Conclusion --- p.34 / Chapter 5 --- Theory on GBAW --- p.35 / Chapter 5.1 --- Introduction --- p.35 / Chapter 5.2 --- Notations and Definitions --- p.36 / Chapter 5.3 --- Minimality and Duality --- p.37 / Chapter 5.4 --- Topological Property of GBAW patterns --- p.41 / Chapter 5.5 --- Experimental Results --- p.47 / Chapter 5.6 --- Conclusion --- p.51 / Chapter 6 --- Multi-way GBAW Partitioning Scheme --- p.52 / Chapter 6.1 --- Introduction --- p.52 / Chapter 6.2 --- Algorithm of GBAW Partitioning Scheme --- p.55 / Chapter 6.3 --- Experimental Results --- p.56 / Chapter 6.4 --- Conclusion --- p.63 / Chapter 7 --- Conclusion --- p.64 / Bibliography --- p.66

Typescript (photocopy). / Digitized by Kansas Correctional Industries

Lo Wing Hang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 60-61). / Abstracts in English and Chinese. / Abstract --- p.i / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Preliminaries --- p.5 / Chapter 2.1 --- Backgrounds and Definitions --- p.5 / Chapter 2.1.1 --- Boolean Network --- p.5 / Chapter 2.1.2 --- Transitive Fanin and Fanout Cone --- p.6 / Chapter 2.1.3 --- Controlling and Sensitizing Values --- p.6 / Chapter 2.1.4 --- Stuck-at Faults and Test Generation --- p.6 / Chapter 2.1.5 --- Mandatory Assignments --- p.8 / Chapter 2.2 --- Review of ATPG-based Rewiring --- p.9 / Chapter 3 --- Improved Single-Pass Rewiring Scheme Using Inconsistent Assignments --- p.14 / Chapter 3.1 --- Introduction --- p.14 / Chapter 3.2 --- Overview of FIRE --- p.15 / Chapter 3.3 --- Alternative Wire Identification Method --- p.17 / Chapter 3.3.1 --- Identifying Candidate Wires --- p.17 / Chapter 3.3.2 --- Redundancy Test on Candidate Wire --- p.18 / Chapter 3.4 --- Redundancy Identification Using Inconsistent Assignments --- p.21 / Chapter 3.5 --- Experimental Results --- p.26 / Chapter 3.6 --- Conclusions --- p.28 / Chapter 4 --- Improving Circuit Partitioning With Rewiring Techniques --- p.29 / Chapter 4.1 --- Introduction --- p.29 / Chapter 4.2 --- Implementation of Rewiring Schemes --- p.31 / Chapter 4.3 --- Coupling Partitioning Algorithm With Rewiring Techniques --- p.33 / Chapter 4.4 --- Experimental Results --- p.37 / Chapter 4.5 --- Conclusions --- p.43 / Chapter 5 --- Circuit Logic Level Reduction by Rewiring for FPGA Mapping --- p.45 / Chapter 5.1 --- Introduction --- p.45 / Chapter 5.2 --- Overview of the Technology Mapping Problem --- p.47 / Chapter 5.2.1 --- Problem Formulation --- p.47 / Chapter 5.2.2 --- FlowMap Algorithm Outline --- p.49 / Chapter 5.3 --- Logic Level Reduction by Rewiring Transformations --- p.51 / Chapter 5.4 --- Experimental Results --- p.54 / Chapter 5.5 --- Conclusions --- p.57 / Chapter 6 --- Conclusions and Future Works --- p.58 / Bibliography --- p.60

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No description available.

Very Large Scale Integration (VLSI) deals with systems complexity rather than transistor size or circuit performance. VLSI design methodology is supported by Computer Aided Design (CAD) and Design Automation (DA) tools, which help VLSI designers to implement more complex and guaranteed designs. The increasing growth in VLSI complexity dictates a hierarchical design approach and the need for hardware DA tools. This paper discusses the generalized Design Procedure for CAD circuit design; the commercial CADs offered by CALMA and the Caesar System, supported by the Berkeley design tools. A complete design of a Content Addressable Memory (CAM) cell, using the Caesar system, supported by Berkeley CAD tools, is illustrated.

Sze, Chin Ngai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 80-84) and index. / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / Curriculum Vitae --- p.iv / List of Figures --- p.ix / List of Tables --- p.xii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation and Aims --- p.1 / Chapter 1.2 --- Contribution --- p.8 / Chapter 1.3 --- Organization of Dissertation --- p.10 / Chapter 2 --- Definitions and Notations --- p.11 / Chapter 3 --- Literature Review --- p.15 / Chapter 3.1 --- Logic Reconstruction --- p.15 / Chapter 3.1.1 --- SIS: A System for Sequential and Combinational Logic Synthesis --- p.16 / Chapter 3.2 --- ATPG-based Alternative Wiring --- p.17 / Chapter 3.2.1 --- Redundancy Addition and Removal for Logic Optimization --- p.18 / Chapter 3.2.2 --- Perturb and Simplify Logic Optimization --- p.18 / Chapter 3.2.3 --- REWIRE --- p.21 / Chapter 3.2.4 --- Implication-tree Based Alternative Wiring Logic Trans- formation --- p.22 / Chapter 3.3 --- Graph-based Alternative Wiring --- p.24 / Chapter 4 --- Implication Based Alternative Wiring Logic Transformation --- p.25 / Chapter 4.1 --- Source Node Implication --- p.25 / Chapter 4.1.1 --- Introduction --- p.25 / Chapter 4.1.2 --- Implication Relationship and Implication-tree --- p.25 / Chapter 4.1.3 --- Selection of Alternative Wire Based on Implication-tree --- p.29 / Chapter 4.1.4 --- Implication-tree Based Logic Transformation --- p.32 / Chapter 4.2 --- Destination Node Implication --- p.35 / Chapter 4.2.1 --- Introduction --- p.35 / Chapter 4.2.2 --- Destination Node Relationship --- p.35 / Chapter 4.2.3 --- Destination Node Implication-tree --- p.39 / Chapter 4.2.4 --- Selection of Alternative Wire --- p.41 / Chapter 4.3 --- The Algorithm --- p.43 / Chapter 4.3.1 --- IB AW Implementation --- p.43 / Chapter 4.3.2 --- Experimental Results --- p.43 / Chapter 4.4 --- Conclusion --- p.45 / Chapter 5 --- Graph Based Alternative Wiring Logic Transformation --- p.47 / Chapter 5.1 --- Introduction --- p.47 / Chapter 5.2 --- Notations and Definitions --- p.48 / Chapter 5.3 --- Alternative Wire Patterns --- p.50 / Chapter 5.4 --- Construction of Minimal Patterns --- p.54 / Chapter 5.4.1 --- Minimality of Patterns --- p.54 / Chapter 5.4.2 --- Minimal Pattern Formation --- p.56 / Chapter 5.4.3 --- Pattern Extraction --- p.61 / Chapter 5.5 --- Experimental Results --- p.63 / Chapter 5.6 --- Conclusion --- p.63 / Chapter 6 --- Logic Optimization by GBAW --- p.66 / Chapter 6.1 --- Introduction --- p.66 / Chapter 6.2 --- Logic Simplification --- p.67 / Chapter 6.2.1 --- Single-Addition-Multiple-Removal by Pattern Feature . . --- p.67 / Chapter 6.2.2 --- Single-Addition-Multiple-Removal by Combination of Pat- terns --- p.68 / Chapter 6.2.3 --- Single-Addition-Single-Removal --- p.70 / Chapter 6.3 --- Incremental Perturbation Heuristic --- p.71 / Chapter 6.4 --- GBAW Optimization Algorithm --- p.73 / Chapter 6.5 --- Experimental Results --- p.73 / Chapter 6.6 --- Conclusion --- p.76 / Chapter 7 --- Conclusion --- p.78 / Bibliography --- p.80 / Chapter A --- VLSI Design Cycle --- p.85 / Chapter B --- Alternative Wire Patterns in [WLFOO] --- p.87 / Chapter B.1 --- 0-local Pattern --- p.87 / Chapter B.2 --- 1-local Pattern --- p.88 / Chapter B.3 --- 2-local Pattern --- p.89 / Chapter B.4 --- Fanout-reconvergent Pattern --- p.90 / Chapter C --- New Alternative Wire Patterns --- p.91 / Chapter C.1 --- Pattern Cluster C1 --- p.91 / Chapter C.1.1 --- NAND-NAND-AND/NAND;AND/NAND --- p.91 / Chapter C.1.2 --- NOR-NOR-OR/NOR;AND/NAND --- p.92 / Chapter C.1.3 --- AND-NOR-OR/NOR;OR/NOR --- p.95 / Chapter C.1.4 --- OR-NAND-AND/NAND;AND/NAND --- p.95 / Chapter C.2 --- Pattern Cluster C2 --- p.98 / Chapter C.3 --- Pattern Cluster C3 --- p.99 / Chapter C.4 --- Pattern Cluster C4 --- p.104 / Chapter C.5 --- Pattern Cluster C5 --- p.105 / Glossary --- p.106 / Index --- p.108