This thesis presents a bio-signal recording system with offset cancellation and a low power comparator. The recording of bio-signal requires high-gain amplification before recording, to match the input to the range of the analog to digital converter (ADC); interference could be a problem if it causes the amplifier to reach saturation, leaving the recording inoperable (i.e., blank) until it returns to its normal state. The proposed system can monitor the amplifier output, and reset the amplifier output to a point near the center of its dynamic range before the amplifier output leaves its dynamic range. The proposed system provides discrete compensation voltages to cancel the offset voltage, and thereby avoids the shortcomings of conventional filters. Furthermore, a low power and low offset voltage comparator for low current operation is proposed. It is suitable for the clock controller in a sampled bio-signal acquisition system. The measured current consumption of the comparator is less than 130 nA, and the offset voltage is 2 mV. The proposed recording system and comparator have been implemented in the TSMC (Taiwan Semiconductor Manufacturing Company) 0.35£gm 2P4M CMOS process technology to verify the simulation results as well as the correctness of the proposed architecture.

With technology increasingly and the needs of high performance and multiple functionalities, power dissipation has be a bottleneck in microprocessors. And clock power is the most percentage of total power dissipation. In our thesis, we will provide an effective clock gating methodology that has not more overhead possibly to decrease total power dissipations based on SIMD 3D vertex shader. Except for classify all instructions according the instruction flow, we also consider the relationship of pipeline stage and are based on register bank to control execution units more flexibility. Using clock gating not only can decrease clock power, but also decrease the power of hardware modules succeed the registers with clock gating that be controlled. In our thesis, we will analysis which clock gating version is suitable because there is not definitely to disable the clock of all pipeline registers of all pipeline stages and hold all opportunities that can disable the clock. We will explain on experimental results and show the final low power version. With experimental results, the clock gating methodology that we bring can decrease almost 30% power with increase less than 2% area. And collection of instruction schedule algorithm for high performance that can decrease 41% energy at most. In new version of four vertexes execute sequentially, using clock gating can also decrease almost 10% power dissipation. And collection of instruction schedule algorithm for this version not only has better performance result but also can decrease 16% energy at most.

This thesis includes two topics. The first topic is an ADFS¡]All Digital Frequency Synthesizer¡^using a Flying Adder architecture. The second one is a low-power and low-latency 2-dimensional bypassing signed multiplier. In the first topic, the ADFS is implemented by only using the standard cell library of TSMC¡]Taiwan Semiconductor Manufacturing Company¡^0.18 £gm 1P6M CMOS process. The turn-around time is effectively reduced. Furthermore, the portability and reusability of the proposed design is significantly enhanced. The design provides stable clock signals with fast switching time. In the second topic, the proposed multiplier is carried out by Baugh-Wooley algorithm using 2-dimensional bypassing units. The proposed bypassing units automatically skip redundant signal transitions when either the horizontally¡]row¡^partial products or vertically¡]column¡^operands are zero.

With the rapid progress in manufacturing technology, the chip design is more and more complicated day by day. As a result, the circuit design with standard cell library becomes more significant. Standard cell is universally applied to cell-based design and the designer can complete their design quickly by using of the elements in standard cell library through cell-based design flow. Therefore, it is indispensable for VLSI design to utilize standard cell library for circuit design. Moreover, the low power design is getting increasingly important in the circuit design. Therefore, we design the cells with particular function and add them into the standard cell library so that the low power design can be more well-designed. In this thesis, we design and and the transmission gate into the standard cell library. In addition, we design two types of standard cells with TSMC 0.13£gm technology: a low-overhead latch and a modified transmission-gate based full adder. They are applied to design different low power multipliers with cell-based design flow and full custom design flow. Experimental results show that our proposed standard cells can reduce the power consumption of the entire multiplier efficiently.

The modern handheld devices have become smaller and more complex nowadays. However, the requirements for its performance and functions have also become higher, which means that it needs more power consumption. Therefore, the essential issue that we are facing now is to reduce the power consumption in order to fit the capacity of the batteries. In the current system level design, there is no presentable commercial tool for designers to estimate the power consumption of the system. This thesis proposes a framework for system level power estimation, which allows the users to add the power models of these modules developed by them in the system level. Moreover, the power models of CPU, memory and bus are also provided. Besides the power models and convenient method to modify these models, a power management unit is also provided. With this unit, the designers can use different power management policies to manage the system¡¦s power consumption and decide its power efficiency. In this thesis, the framework is constructed under the environment of SystemC, so the users can alternate the power model and power management policy rapidly. By using this framework, the designers can more conveniently and rapidly estimate the system¡¦s power consumption and improve the system¡¦s architecture. Therefore, it can fast examine the advantages and disadvantages of various power models and power management policies.

As semiconductor technology continues to scale, energy-efficiency and power consumption have become the dominant design limitations, especially, for embedded and portable systems. Conventional worst-case design is highly inefficient from an energy perspective. In this dissertation, we propose techniques for adaptivity at the architecture and circuit levels in order to remove some of these inefficiencies. Specifically, this dissertation focuses on research contributions in two areas: 1) the development of SRAM models and circuitry to enable an intra-array voltage island approach for dealing with large random process variation; and 2) the development of low-energy digital signal processing (DSP) techniques based on controlled timing error acceptance. In the presence of increased process variation, which characterizes nanometer scale CMOS technology, traditional design strategies result in designs that are overly conservative in terms of area, power consumption, and design effort. Memory arrays, such as SRAM-based cache, are especially vulnerable to process variation, where the penalty is a power and bit-cell increase needed to satisfy a variety of noise margins. To improve yield and reduce power consumption in large SRAM arrays, we propose an intra-array voltage island technique and develop circuits that allow for a cost-effective deployment of this technique to reduce the impact of process variation. The voltage tuning architecture makes it possible to obtain, on average, power consumption reduction of 24% iso-area in the active mode, and the leakage power reduction up to 52%, and, on average, of 44% iso-area in the sleep mode. Alternatively, bitcell area can be reduced up to 50% iso-power compared to the existing design strategy. In many portable and embedded systems, signal processing (SP) applications are dominant energy consumers. In this dissertation we investigate the potential of error-permissive design strategies to reduce energy consumption in such SP applications. Conventional design strategies are aimed at guaranteeing timing correctness for the input data that triggers the worst-case delay, even if such data occurs infrequently. We notice that an intrinsic notion of quality floor characterizes SP applications. This provides the opportunity to significantly reduce energy consumption in exchange for a limited signal quality reduction by strategically accepting small and infrequent timing errors. We propose both design-time and run-time techniques to carefully control the quality-energy tradeoff under scaled VDD. The basic philosophy is to prevent signal quality from severe degradation, on average, by using data statistics. We introduce techniques for: 1) static and dynamic adjustment of datapath bitwidths, 2) design-time and run-time reordering of computations, 3) protection of important algorithm steps, and 4) exploiting the specific patterns of errors for low-cost post-processing to minimize signal quality degradation. We demonstrate the effectiveness of the proposed techniques on a 2D-IDCT/DCT design, as well as several digital filters for audio and image processing applications. The designs were synthesized using a 45nm standard cell library with energy and delay evaluated using NanoSim and VCS. Experiments show that the introduced techniques enable 40~70% energy savings while only adding less than 6% area overhead when applied to image processing and filtering applications. / text

Recent interest in approximate computation is driven by its potential to achieve large energy savings. We formally demonstrate an optimal way to reduce energy via voltage over-scaling at the cost of errors due to timing starvation in addition. A fundamental trade-off between error frequency and error magnitude in a timing-starved adder has been identified. We introduce a formal model to prove that for signal processing applications using a quadratic signal-to-noise ratio error measure, reducing bit-wise error frequency is sub-optimal. Instead, energy-optimal approximate addition requires limiting maximum error magnitude. Intriguingly, due to possible error patterns, this is achieved by reducing carry chains significantly below what is allowed by the timing budget for a large fraction of sum bits, using an aligned, fixed internal-carry structure for higher significance bits. We further demonstrate that remaining approximation error is reduced by realization of conditional bounding (CB) logic for lower significance bits. A key contribution is the formalization of an approximate CB logic synthesis problem that produces a rich space of Pareto-optimal adders with a range of quality-energy trade-offs. We show how CB logic can be customized to result in over- and under-estimating approximate adders, and how a dithering adder that mixes them produces zero-centered error distributions, and, in accumulation, a reduced-variance error. This work demonstrates synthesized approximate adders with energy up to 60% smaller than that of a conventional timing-starved adder, where a 30% reduction is due to the superior synthesis of inexact CB logic. When used in a larger system implementing an image-processing algorithm, energy savings of 40% are possible. / text

The design, fabrication, and in-vivo testing of an implantable device to measure the pressure-volume (PV) relationship in the hearts of conscious, untethered rats is presented. Volume is measured using a tetrapolar catheter positioned in the left-ventricle which emits a 20kHz current field across the LV blood pool and parallel heart tissue and measures the resulting voltage. The admittance method is used to instantaneously remove the contribution of the parallel heart muscle and Wei’s non-linear blood conductance-to-volume equation is used to calculate volume. Pressure is measured with a strain gauge sensor at the tip of the catheter. The implant was designed to be small, light, and low-power. An average implant occupies 5 cm3, weighs 8g, and on a single charge collects data for 2 months taking 43 samples per day. Collected data is transmitted wirelessly via RF to a base station where it is recorded. The functionality of the implant and measurement system was verified in six rat experiments. In all experiments, ambulatory PV loops were measured on implantation day. Viable pressure data was recorded for 11 days in one rat; in another rat viable admittance data was collected for 10 days. Changing catheter position and non-constant blood resistivity are considered as sources of error in the volume measurement. Pressure drift due to changing atmospheric pressure is considered as a source of error in the pressure measurement. Lastly, alternative uses for the implant and directions for future improvement are considered. / text

This paper is intended to be a resource for programmers needing to optimize a DSP’s power consumption strictly through software. The paper will provide a basic introduction into power consumption background, measurement techniques, and then go into the details of power optimization, focusing on three main areas: algorithmic optimization, taking advantage of hardware features (low power modes, clock control, and voltage control), and data flow optimization with a discussion into the functionality and power considerations when using fast SRAM type memories (common for cache) and DDR SDRAM. This work includes examples and results as tested on Freescale’s current state of the art Digital Signal Processors. / text

Floating-point computer arithmetic units are used for modern-day computers for 2D/3D graphic and scientific applications due to their wider dynamic range than a fixed-point number system with the same word-length. However, the floating-point arithmetic unit has larger area, power consumption, and latency than a fixed-point arithmetic unit. It has become a big issue in modern low-power processors due to their limited power and performance margins. Therefore, fused architectures have been developed to improve floating-point operations. This dissertation introduces new improved fused architectures for add-subtract, sum-of-squares, and magnitude operations for graphics, scientific, and signal processing. A low-power dual-path fused floating-point add-subtract unit is introduced and compared with previous fused add-subtract units such as the single path and the high-speed dual-path fused add-subtract unit. The high-speed dual-path fused add-subtract unit has less latency compared with the single-path unit at a cost of large power consumption. To reduce the power consumption, an alternative dual-path architecture is applied to the fused add-subtract unit. The significand addition, subtraction and round units are performed after the far/close path. The power consumption of the proposed design is lower than the high-speed dual-path fused add-subtract unit at a cost in latency; however, the proposed fused unit is faster than the single-path fused unit. High-performance and low-power floating-point fused architectures for a two-term sum-of-squares computation are introduced and compared with discrete units. The fused architectures include pre/post-alignment, partial carry-sum width, and enhanced rounding. The fused floating-point sum-of-squares units with the post-alignment, 26 bit partial carry-sum width, and enhanced rounding system have less power-consumption, area, and latency compared with discrete parallel dot-product and sum-of-squares units. Hardware tradeoffs are presented between the fused designs in terms of power consumption, area, and latency. For example, the enhanced rounding processing reduces latency with a moderate cost of increased power consumption and area. A new type of fused architecture for magnitude computation with less power consumption, area, and latency than conventional discrete floating-point units is proposed. Compared with the discrete parallel magnitude unit realized with conventional floating-point squarers, an adder, and a square-root unit, the fused floating-point magnitude unit has less area, latency, and power consumption. The new design includes new designs for enhanced exponent, compound add/round, and normalization units. In addition, a pipelined structure for the fused magnitude unit is shown. / text