Three improved operational amplifiers with low voltage and rail-to-rail constant are proposed. Two of the amplifiers are modified from the amplifier with a level shifting circuit. One improved amplifier has fewer devices, higher speed, and reduced area and the other improved amplifier is added an additional adjustable gain. The third amplifier is a floating voltage controlled voltage source (FVCVS) amplifier, which has reduced area and improved frequency response. The first two level shifting operational amplifiers are designed in a 0.5£gm UMC CMOS process. They use about half number of devices. The supply voltage is 1.3V, and the current consumes just only 22.6¢H of the original circuits. The unity gain frequency increases 56.8%. The slew rate, CMRR and PSRR are higher. The 2nd amplifier still has a rail-to-rail constant gm; however, the gm can be adjusted. The third amplifier uses the 0.35£gm UMC CMOS process with 1.2V operating voltage. The gain-bandwidth product is 53.8¢H larger than the original circuits. No frequency compensation is used and the devices are fewer. The results are obtained in HSPICE simulation.

A rail-to-rail op-amp with high stability over temperature variation at 1-V supply voltage is presented in this thesis. It incorporates a modified CM adapter and a modified bandgap reference. First, the modified CM adapter utilizes a level-shifting technique to shift the input common mode voltage of 0-1 V to the level below 0.1 V. By introducing this circuit as the front-end block of the proposed op-amp, the PMOS differential input stage can be operated appropriately with the rail-to-rail input common mode range. Second, the modified bandgap reference that combines two voltages with opposite temperature coefficients generates a temperature-insensitive bias current to the input stage. Besides, by the technique of cascading a diode with an additional BJT, the junction area of the original diodes can be reduced and in the actual application, fewer parallel-connected BJTs are needed. The two circuits are applied to the proposed op-amp operated at 1-V supply voltage in TSMC 1P4M 0.35£gm CMOS technology. At 25¢J, the dc gain is 78.9 dB and unity-gain bandwidth is 3.73 MHz. The phase margin is 42.9¢X. For the temperature from 0¢J to 75¢J, the frequency response is temperature-insensitive and the dc gain variation is 2dB. The layout view of the proposed op-amp is also presented and the area is 0.2 mm2.

Thesis (M.S.)--University of Missouri-Columbia, 2003. / Typescript. Includes bibliographical references (leaves 132-133). Also available on the Internet.

Thesis (M.S.)--University of Missouri-Columbia, 2003. / Typescript. Includes bibliographical references (leaves 132-133). Also available on the Internet.

Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2004. Directed by Abhijit Chatterjee. / Vita. Includes bibliographical references (leaves 127-145).

Thesis (Ph. D.)--University of Washington, 2003. / Vita. Includes bibliographical references (leaves 96-101).

Thesis (Ph. D.)--University of Texas at Austin, 2001. / Vita. Includes bibliographical references (leaves 99-104). Available also in a digital version from Dissertation Abstracts.

As the world moves towards a more sustainable development, the energy coming from fossil fuels still produces the greenhouse gases that threaten the world’s climate. The UK government has established targets for the penetration of renewable energy generation and low-carbon alternatives for the electricity production. One of these technologies is microgeneration. In 2006, the UK government launched the Microgeneration Strategy pushing forward micro and small-scale generation as a supplementary source of energy for the country’s growing electricity demand. The proposal is focused on several technologies, including micro-wind and micro-PV, among others. These microgeneration technologies are now a reality and widespread across the distribution networks. Therefore, the analysis of the impact of these systems connected to distribution grids and the benefits of these technologies, alongside with their negative effects on the network is an important research area. Correct modelling of micro and small-scale renewablebased generation technologies implemented in urban areas, however, is not a simple task, as it requires an adequate representation of highly dispersed and uncontrolled generation systems. These systems are small in size, but high in numbers and usually experience large variations in available renewable energy inputs. This thesis presents aggregate models of urban micro and small-scale PV and wind generation systems, which are connected to low-voltage networks. The thesis analyses impact of urban PV and wind generation on the steady-state network performance (power flows and voltage profiles), taking into account variability of energy inputs. The presented analysis is of particular importance for the analysis of the future of power system supplies, which will have significantly higher penetration levels of renewable-based distributed generation technologies, resulting in a much wider range of interactions between microgeneration systems, loads and transmission/distribution networks. In order to perform this analysis, the resource assessment for urban areas has to be carried out to both quantify the potential for each technology and help in their modelling. This has been a challenge since the aggregation of microgeneration systems is far from simple, as the parameters, performance and size varies between different technologies. A solution presented in this thesis is an approach for simple yet accurate aggregation of microgeneration technologies. This approach allows to quantify and analyse their impact and effect on the power supply systems directly in terms of penetration levels and general technology characteristics.

One of the major limiters to computer systems and systems on chip (SOC) designs is accessing the main memory, which is typically two orders of magnitude slower than the processor. To bridge this gap, modern processors already devote more than half of the on-chip transistors to the last-level cache. Caches have negative impact on area, power, and yield. This research goal is to design caches that operate at lower voltages while enhancing yield. Our strategy is to improve the static noise margin (SNM) and the writability of the conventional six-transistor SRAM cell by reducing the effect of parametric variations on the cell. This is done using a novel circuit that reduces the voltage swing on the word line during read operations and reduces the memory supply voltage during write operations. The proposed circuit increases the SRAM’s SNM and write margin using a single voltage supply that has minimal impacts on chip area, complexity, and timing. A test chip with an 8-kilobyte SRAM block manufactured in 45- nm technology is used to verify the practicality of the contribution and demonstrate the effectiveness of the new circuit’s implementation. Cache organization is one of the most important factors that affect cache design complexity, performance, area, and power. The main architectural choice for caches is whether to implement the tag array using a standard SRAM or using a content addressable memory (CAM). The choice made has far-reaching consequences on several aspects of the cache design, and in particular on power consumption. Our contribution in this area is an in-depth study of the complex tradeoffs of area, timing, power, and design complexity between an SRAM-based tag and a CAM-based one. Our results indicate that an SRAM-based tag design often provides a better overall design point and is superior with respect to energy, especially for interleaved multi-threading processors. Being able to test and screen chips is a key factor in achieving high yield. Most industry standard CAD tools used to analyze fault coverage and generate test vectors require gate level models. However, since caches are typically designed using a transistor-level flow, there is a need for an abstraction step to generate the gate models, which must be equivalent to the actual design (transistor level). The third contribution of the research is a framework to verify that the gate level representation of custom designs is equivalent to the transistor-level design. / text

As process technologies continue their rapid advancement, transistor features are shrinking to almost unimaginable sizes. Some dimensions can be measured at the atomic level. One consequence of these smaller devices is that they have become more susceptible to deviations from nominal than previous process nodes. To illustrate, as few as one hundred atoms determine how much voltage is needed to turn a transistor on and off. With over two billion transistors on a single chip, it is easy to imagine how even the tiniest of variations can affect many transistors throughout the entire chip. To compensate for these deviations, chip designers add margin to their designs. Even more margin is then added for increased safety. All of this margin leads to chips that are slower than a nominal design would be. At the other end of the spectrum, these same deviations might result in chips that are faster than needed. However, faster is not always better, as these faster chips usually require more power. Even worse, these deviations sometimes produce chips that are both slower and use more power than a nominal design. TuneChip is designed to mitigate the effects of these process variations by speeding up areas of a chip that need to run faster while at the same time reducing power in parts of a chip that are operating faster than needed. TuneChip attacks the variation problem by changing the voltage on small areas of the chip in response to the type of variation for that particular area. Since voltage has a strong relationship to the speed of a chip, TuneChip can increase the speed of areas that need to go faster. At the same time, TuneChip can decrease the speed of other areas on the chip that are too fast. Even more important than speed for current designs, though, is power. Changing the voltage has a quadratic relationship with the amount of power consumed by that device. Specifically, a 10% reduction in supply voltage yields a 20% reduction in energy. Moreover, it is not only battery powered devices that benefit from reduced energy consumption; some high performance designs are limited by how much they can cool the chip. Cost-effective cooling technology is not scaling at anywhere near the same rate as transistor geometries. Reducing a chip’s power consumption also reduces excess heat. In order to selectively change the voltage of specific areas of the design, TuneChip starts by partitioning the chip into smaller blocks. A dual voltage design style with two voltage grids spans the entire chip. In order to best react to variations particular to an individual chip, each block is assigned a supply voltage only after manufacturing. First, the chip is tested at high voltage and high power in order to verify the correct functionality of that chip. If the chip passes its functionality testing, each individual block is tested to determine how fast it is operating. Blocks that need to run faster are configured to connect to the high supply voltage grid, and blocks that are able to run slower are configured to connect to the low supply voltage grid. The configurable block supply voltage connection is accomplished with pmos pass transistors that act like switches. By having only one pmos pass transistor switch turned on at a time, each block has a choice of two supply voltages. / text