The objective of manufacturing test is to separate the faulty circuits from the good circuits after they have been manufactured. Three problems encompassed by this task will be mentioned here. First, the reduction of the power consumed during test. The behavior of the circuit during test is modified due to scan insertion and other testing techniques. Due to this, the power consumed during test can be abnormally large, up to several times the power consumed during functional mode. This can result in a good circuit to fail the test or to be damaged due to heating. Second, how to modify the design so that it is easily testable. Since not every possible digital circuit can be tested properly it is necessary to modify the design to alter its behavior during test. This modification should not alter the functional behavior of the circuit. An example of this is test point insertion, a technique aimed at reducing test time and decreasing the number of faulty circuits that pass the test. Third, the creation of a test set for a given design that will both properly accomplish the task and require the least amount of time possible to be applied. The precision in separation of faulty circuits from good circuits depends on the application for which the circuit is intended and, if possible, must be maximized. The test application time is should be as low as possible to reduce test cost. This dissertation contributes to the discipline of manufacturing test and will encompass advances in the afore mentioned areas. First, a method to reduce the power consumed during test is proposed. Second, in the design modification area, a new algorithm to compute test points is proposed. Third, in the test set creation area, a new algorithm to reduce test set application time is introduced. The three algorithms are scalable to current industrial design sizes. Experimental results for the three methods show their effectiveness.

<p>Advances in semiconductor technology and design automation methods have introduced a new era for electronic products. With design sizes in millions of logic gates and operating frequencies in GHz, defects-per-million rates continue to increase, and defects are manifesting themselves in subtle ways. Traditional test methods are not sufficient to guarantee product quality and diagnostic programs cannot rapidly locate the root cause of failure in large systems. Therefore, there is a need for efficient fault diagnosis methods that can provide quality assurance, accelerate new product release, reduce manufacturing cost, and increase product yield.</p><p>This thesis research is focused on fault-insertion test (FIT) and fault diagnosis at the board and system levels. FIT is a promising technique to evaluate system reliability and facilitate fault diagnosis. The error-handling mechanism and system reliability can be assessed in the presence of intentionally inserted faults, and artificial faulty scenarios can be used as references for fault diagnosis. However, FIT needs to be deployed under constraints of silicon area, design effort, availability of equipment, and what is actually possible to test from one design to the next. In this research, physical defect modeling is developed to provide an efficient solution for fault-insertion test. Artificial faults at the pin level are created to represent physical defects inside devices. One pin-level fault is able to mimic the erroneous behaviors caused by multiple internal defects. Therefore, system reliability can be evaluated in a more efficient way.</p><p>Fault diagnosis is a major concern in the semiconductor industry. As the density and complexity of systems increase relentlessly and the subtle effects of defects in nanometer technologies become more pronounced, fault diagnosis becomes difficult, time-consuming, and ineffective. Diagnosis of functional failure is especially challenging. Moreover, the cost associated with board-level diagnosis is escalating rapidly. Therefore, this thesis presents a multi-pronged approach to improve the efficiency and accuracy of fault diagnosis, including the construction of a diagnostic framework with FIT and Bayesian inference, the extraction of an effective fault syndrome (error flow), the selection of diagnosis-oriented fault-insertion points, and the application of machine learning for intelligent diagnosis.</p><p>First, in the inference-based diagnosis framework, FIT is used to create a large number of faulty samples and derive the probabilities needed for the application of Bayes' theorem; next the probability of a fault candidate being the root cause can be inferred based on the given fault syndromes. Results on a case study using an open-source RISC system-on-chip demonstrate the feasibility and effectiveness of the proposed approach. Second, the concept of error flow is proposed to mimic actual data propagation in a circuit, and thus it reflects the logic functionality and timing behavior of circuits. With this additional information, more fault syndromes are distinguishable. Third, diagnosis-oriented fault-insertion points are defined and selected to create the representative and distinguishable syndromes. Finally, machine learning approaches are used to facilitate the debug and repair process. Without requiring the need to understand the complex functionality of the boards, an intelligent diagnostic system is designed to automatically exploit the diagnostic knowledge available from past cases and make decisions on new cases.</p><p>In summary, this research has investigated efficient means to perform fault-insertion test and developed automated and intelligent diagnosis methods targeting functional failures at the board level. For a complex circuit board currently in production, the first-time success rate for diagnosis has been increased from 35.63% to 72.64%. It is expected to contribute to quality assurance, product release acceleration, and manufacturing-cost reduction in the semiconductor industry.</p> / Dissertation

The continuing trend of miniaturization in semiconductor devices has enabled the integration of complex functionalities on-chip, leading to a proliferation of wireless devices for both mobile and in-office applications. The use of scaled CMOS technologies for high-frequency wireless devices is posing daunting technological challenges, both in the design and post-manufacture testing of such devices. The issue of device power consumption and heat dissipation is also dominating future wireless transceiver designs. This is driven by the trend of increasing operating speeds coupled with dense integration of multi-mode functionalities onto compact form-factors on-chip. In this thesis, a framework for reliable low-power operation of wireless devices is presented. The presented approaches significantly reduce device test costs during production, and operate the device at very low power consumption levels during field operation of the device. Low-cost test, diagnosis, and tuning techniques to reduce to reduce test cost of devices and operational reliability in field. To reduce device power consumption during field operation, adaptation is performed continuously while ensuring that system-level performance metrics are never violated. This approach has direct implications for boosting the battery life of portable wireless devices while ensuring their operational reliability.

Bio-composites are increasing in demand due to governmental incentives across the globe for both environmental and human health reasons. The ideal bio-composite is renewable, recyclable, available, and non-toxic. To properly engineer bio-composite products, the physical properties of the fiber as well as fiber/matrix interactions must be known. The problem lies in the fact that many suitable natural fibers are not currently available in a material form that may be easily worked with. This research investigates methods to process raw kenaf (hibiscus cannabinus) on a scale that allows researchers to make more consistent samples for testing. Though kenaf is highlighted, these processing methods may be applied to any natural fiber. The raw fibers are processed into kenaf chopped strand mats (KCSM) by adapting basic paper-making techniques. KCSM exhibit paper-like qualities and mechanical properties and provide a material of uniform thickness for use in composite parts. Also presented are a basic understanding of natural fiber constituents and effects of mechanical and co-mechanical treatments on those constituents. To test KCSM, samples are made for the ASTM D3039 tensile testing and for testing in a dynamic material analyzer (DMA). Both mechanically and chemo-mechanically processed samples are made for the purpose of comparison. Also, I-beam bridges are built with KCSM to demonstrate how KCSM may be used to create a structure. This is spurred on by the annual SAMPE bridge competition that includes special categories for natural fiber beams. The lay-up procedure is shown in detail to provide a framework that future competitors may use to build quality I-beams for this competition. The properties obtained by using the KCSM are competitive with other reported properties for kenaf-based composites. A kenaf I-beam demonstrates a strength-to-weight ratio that is 65% of a berglass I-beam built to the same dimensions. Trade-os of using KCSM are the random 2d-fiber orientation and brittle failure, which are not usually desirable in composite components. The chemically treated samples indicate a higher degree of crystallinity but demonstrate inferior mechanical properties when compared to the untreated samples.