The movement to smart mobile connected devices which consolidate functions of traditionally separate devices is driving innovation in System-on-chips (SoCs). One of the innovations helping to meet the current needs of SoCs is the integration of larger memory with the processor, and with this, comes the challenge of testing all the memory cells. The programmable memory BIST offers a flexible approach to designers and testers because it allows the memory test algorithms to be updated when new memory fault models are discovered. But this flexibility comes as a trade-off to area as the BIST circuitry needs to be integrated next to the memory array. This report proposes enhancements to an existing design that will improve flexibility by enhancing the address generation schemes while simultaneously eliminating the need for an auxiliary memory in cases where a Type-1 NPSF background will be used. A comparison of the base design to the proposed design shows the address and data generation improvements can be achieved with only 1.8% increase in area with an 8KB memory. / text

This paper describes various approaches to hardware testing semiconductor memory. We describe the priciple of basic memory types, the way which each of them stores information and their comunication protocol. Following part deals with common failures which may occur in the memory.  The section also describes the implementation of memory model and tester designed in VHDL language. It is possible to inject some errors into memory, which are later detected by the tester. The final section shows the response of tester to various error types according to used error detection method. The paper is especially focused on failure detection by variants of march test.

This work deals with COMBO2 card interconnect and memory devices testing. In the beginning of the paper, some existing testing algorithms for interconnect and RAM memories testing are introduced. This work is devoted to proposal of generic architecture for interconnect and memory devices testing. The proposed architecture is optimized for FPGA implementation.