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Situational Wireless Awareness NetworkScheidemantel, Austin, Alnasser, Ibrahim, Carpenter, Benjamin, Frost, Paul, Nettles, Shivhan, Morales, Chelsie 10 1900 (has links)
ITC/USA 2010 Conference Proceedings / The Forty-Sixth Annual International Telemetering Conference and Technical Exhibition / October 25-28, 2010 / Town and Country Resort & Convention Center, San Diego, California / The purpose of this paper is to explain the process to implementing a wireless sensor network in order to improve situational awareness in a dense urban environment. Utilizing a system of wireless nodes with Global Positioning System (GPS) and heart rate sensors, a system was created that was able to give both position and general health conditions. By linking the nodes in a mesh network line of sight barriers were overcome to allow for operation even in an environment full of obstruction.
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Deadlock Free Routing inMesh Networks on Chip with RegionsHolsmark, Rickard January 2009 (has links)
<p>There is a seemingly endless miniaturization of electronic components, which has enabled designers to build sophisticated computing structureson silicon chips. Consequently, electronic systems are continuously improving with new and more advanced functionalities. Design complexity ofthese Systems on Chip (SoC) is reduced by the use of pre-designed cores. However, several problems related to the interconnection of coresremain. Network on Chip (NoC) is a new SoC design paradigm, which targets the interconnect problems using classical network concepts. Still,SoC cores show large variance in size and functionality, whereas several NoC benefits relate to regularity and homogeneity.</p><p>This thesis studies some network aspects which are characteristic to NoC systems. One is the issue of area wastage in NoC due to cores of varioussizes. We elaborate on using oversized regions in regular mesh NoC and identify several new design possibilities. Adverse effects of regions oncommunication are outlined and evaluated by simulation.</p><p>Deadlock freedom is an important region issue, since it affects both the usability and performance of routing algorithms. The concept of faultyblocks, used in deadlock free fault-tolerant routing algorithms has similarities with rectangular regions. We have improved and adopted one suchalgorithm to provide deadlock free routing in NoC with regions. This work also offers a methodology for designing topology agnostic, deadlockfree, highly adaptive application specific routing algorithms. The methodology exploits information about communication among tasks of anapplication. This is used in the analysis of deadlock freedom, such that fewer deadlock preventing routing restrictions are required.</p><p>A comparative study of the two proposed routing algorithms shows that the application specific algorithm gives significantly higher performance.But, the fault-tolerant algorithm may be preferred for systems requiring support for general communication. Several extensions to our work areproposed, for example in areas such as core mapping and efficient routing algorithms. The region concept can be extended for supporting reuse ofa pre-designed NoC as a component in a larger hierarchical NoC.</p>
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Deadlock Free Routing in Mesh Networks on Chip with RegionsHolsmark, Rickard January 2009 (has links)
There is a seemingly endless miniaturization of electronic components, which has enabled designers to build sophisticated computing structureson silicon chips. Consequently, electronic systems are continuously improving with new and more advanced functionalities. Design complexity ofthese Systems on Chip (SoC) is reduced by the use of pre-designed cores. However, several problems related to the interconnection of coresremain. Network on Chip (NoC) is a new SoC design paradigm, which targets the interconnect problems using classical network concepts. Still,SoC cores show large variance in size and functionality, whereas several NoC benefits relate to regularity and homogeneity. This thesis studies some network aspects which are characteristic to NoC systems. One is the issue of area wastage in NoC due to cores of varioussizes. We elaborate on using oversized regions in regular mesh NoC and identify several new design possibilities. Adverse effects of regions oncommunication are outlined and evaluated by simulation. Deadlock freedom is an important region issue, since it affects both the usability and performance of routing algorithms. The concept of faultyblocks, used in deadlock free fault-tolerant routing algorithms has similarities with rectangular regions. We have improved and adopted one suchalgorithm to provide deadlock free routing in NoC with regions. This work also offers a methodology for designing topology agnostic, deadlockfree, highly adaptive application specific routing algorithms. The methodology exploits information about communication among tasks of anapplication. This is used in the analysis of deadlock freedom, such that fewer deadlock preventing routing restrictions are required. A comparative study of the two proposed routing algorithms shows that the application specific algorithm gives significantly higher performance.But, the fault-tolerant algorithm may be preferred for systems requiring support for general communication. Several extensions to our work areproposed, for example in areas such as core mapping and efficient routing algorithms. The region concept can be extended for supporting reuse ofa pre-designed NoC as a component in a larger hierarchical NoC.
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Method development for investigation of real effects on flow around vanesMårtensson, Jonathan January 2010 (has links)
<p>In the development of turbo machinery components it's desirable to not spend more time than necessary when setting up aero-thermal calculations to investigate uncertainties in the design. This report aims to describe general thoughts used in the development of an ICEM-mesh script and the possible configurations in the script file which enables the user to build mesh-grids with/without clearance gap at the hub and/or shroud for different blade geometries. It also aims to illustrate the performance analysis made on the Vinci LH2 turbine, a next generation upper stage engine to the Ariane 5 rocket, in which the effect of the tip gap size on the efficiency has been studied.</p><p>The calculations made have shown good agreement with experimental data. The efficiency loss due to the mixing of fluid where leakage flow passes the tip gap, which results in growth of a strong vortex, and the fluid passing the blade tip, with almost no work extracted from it, has shown a quite linear efficiency dependence depending on the tip gap size.</p>
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Method development for investigation of real effects on flow around vanesMårtensson, Jonathan January 2010 (has links)
In the development of turbo machinery components it's desirable to not spend more time than necessary when setting up aero-thermal calculations to investigate uncertainties in the design. This report aims to describe general thoughts used in the development of an ICEM-mesh script and the possible configurations in the script file which enables the user to build mesh-grids with/without clearance gap at the hub and/or shroud for different blade geometries. It also aims to illustrate the performance analysis made on the Vinci LH2 turbine, a next generation upper stage engine to the Ariane 5 rocket, in which the effect of the tip gap size on the efficiency has been studied. The calculations made have shown good agreement with experimental data. The efficiency loss due to the mixing of fluid where leakage flow passes the tip gap, which results in growth of a strong vortex, and the fluid passing the blade tip, with almost no work extracted from it, has shown a quite linear efficiency dependence depending on the tip gap size.
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Implementation and performance analysis of star-based mesh networkHaq, Muhammad January 2011 (has links)
The goal of the thesis is to design the star-based mesh topology by introducing multiple pan-coordinators (hub/switches) under a multipath-fading environment and to improve the data transaction rate of a network which usually gets worst when there is a single pan-coordinator for synchronization of devices in conventional mesh topology; also reduce the hop-count as least as possible. Most of the work has been done on NS-2 network simulator; therefore the research model which has been used here is a simulation model. Altogether 3 simulations have been done. The first scenario is done on a simplest mesh network with a single coordinator and a radio propagation model which has been used is two-ray ground reflection model. The second scenario simulation is similar to the first scenario but in-order to provide multi-path signal fading and highly congested environment the propagation model which has been used this time is shadowing model. The final simulation which has been done is of multiple-star based mesh topology it also uses the similar radio propagation model which has been defined for second scenario. An intensive performance measurement of all the three simulations has been done in terms of transactions made per-second, packet drop rate along with an analysis of packet drop. An hop-count is also measured between star and mesh topology. For multiple star based mesh topology it can be assumed if multiple stars with a routing capability can be used then nodes in a network will be synchronized or re-synchronized with least number of hops in the congested network with a near-by pan-coordinator (hub/switch). One of the major applications of this topology can be automobile manufacturing industry where alot of machines are installed in a congested network and monitoring of every area is mandatory for swift production.
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Thread Smart Home Model / Thread Smart Home ModelSieklik, Ivan January 2017 (has links)
This thesis is focused on smart buildings where communication and automatization technologies are deployed. It includes overview and description of frequently applied network protocols in smart homes and their side by side comparison with an emphasis on Thread networking protocol. The next chapters describe details and parameters of used development boards provided by NXP Semiconductors and their implementation in a smart home model. Subsequent chapters are focused on hardware and software components which are the basis for smart home model’s internal workings. The last chapter highlights how a physical model of a smart home was developed with suggestions for future improvements.
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