Integration of high-K Metal-Insulator-Metal (MIM) capacitors in the Back-end-of-line (BEOL) is a topic of interest for the further development of the process at KTH Royal Institute of Technology. MIM-capacitors benefit from having constant capacitance values over a range of voltages and/or frequencies. One significant limitation in the development of better MIM-capacitors is the temperature consideration for BEOL processes. For the process at KTH Institute of Technology the temperature should not exceed 600 °C, as this would damage underlying devices. This work aims to fabricate aluminium oxide MIM-capacitors as a standard BEOL process performed at low temperature, which has been achieved via atomic layer deposition (ALD). The fabricated aluminium oxide MIM-capacitors had a good quality factor, series resistance and low dissipation. The capacitance for a 10 nm thick aluminium oxide insulator layer was 1 µF/cm2, which exceeds the set requirement. This work also aimed to make ferroelectric aluminium doped hafnium oxide MIM-capacitors using ALD. The doping ratio was varied in ALD as this had been found to affect formation of the ferroelectric crystal phase after a rapid thermal annealing step. Three wafers of 20 nm thick hafnium oxide and differing ratios were found to not be ferroelectric. The intermediate doping ratio was found to appear slightly anti-ferroelectric. A 10 nm thick doped hafnium oxide of intermediate doping was also fabricated and was found to be ferroelectric with a remnant polarisation of 1 µC/cm2. Though this polarisation is relatively small, it shows that top electrode induced strain due to lattice mismatch could be responsible for the ferroelectric properties of the capacitor. The quality of the hafnium based capacitors seemed worse in comparison to the aluminium oxide capacitors, which is suspected to be due to oxygen vacancies, resulting in a high loss tangent. While this first experiment showed promising results, the ferroelectric remnant polarisation should be increased by an order of magnitude and the electrical benchmark values should be improved before these hafnium oxide MIM-capacitors can be used in the BEOL process. / Integratie van high-K MIM-condensatoren in de Back-end-of-line (BEOL) is een onderwerp van belang voor de ontwikkeling van het proces bij de KTH. MIM-condensatoren profiteren van een constante capaciteitswaarde over een reeks spanningen en/of frequenties. Een belangrijke beperking bij de ontwikkeling van betere MIM-condensatoren is het temperatuur limiet voor BEOL-processen. Bij de KTH moet de temperatuur niet hoger zijn dan 600 °C, omdat dit de onderliggende apparaten zou beschadigen. Dit werk heeft tot doel aluminiumoxide MIM-condensatoren te fabriceren als een standaard BEOL-proces met lage temperatuur, en heeft dit inderdaad bereikt via atomaire laagafzetting (ALD). De gefabriceerde aluminiumoxide MIM-condensatoren hadden een goede kwaliteitsfactor, serieweerstand en lage dissipatie. De capaciteit voor een 10 nm dikke aluminiumoxide-isolatorlaag was 1µF/cm2, hoger dan de gestelde eisen. Dit werk was ook gericht op het maken van ferro-elektrische aluminium gedoteerde hafniumoxide MIM-condensatoren met behulp van ALD. De doteringsverhouding werd gevarieerd in ALD, aangezien bleek dat dit de vorming van de ferro-elektrische kristalfase faciliteerde na een snelle thermische gloeistap. Drie wafers van 20 nm dik hafniumoxide en verschillende verhoudingen bleken niet ferro-elektrisch te zijn. De tussenliggende doteringsverhouding bleek enigszins anti-ferro-elektrisch te zijn. Een 10 nm dik gedoteerd hafniumoxide met intermediaire dotering werd ook gefabriceerd en bleek ferro-elektrisch te zijn met een restpolarisatie van 1 µC/cm2. Hoewel deze polarisatie relatief klein is, toont het aan dat de door de topelektrode geïnduceerde spanning als gevolg van roostermismatch verantwoordelijk zou kunnen zijn voor de ferro-elektrische eigenschappen van de condensator. De kwaliteit van de op hafnium gebaseerde isolator leek slechter in vergelijking met die van aluminiumoxide, hetgeen kan worden toegeschreven aan gebrek van zuurstof in het rooster, wat in een groot verlies resulteert. De ferro-elektriciteit moet met een orde van grootte worden verhoogd en de elektrische benchmarks moeten ook verhoogd worden voordat deze hafniumoxide MIM-condensatoren kunnen worden gebruikt in het BEOLproces. Sleutelwoorden: atomaire laagafzetting (ALD), Ferro-elektrisch, Metaal-Isolator- Metaal (MIM) condensator, lage temperatuur, snelle thermische gloeiing.

Metal-insulator-metal (MIM) capacitors are used for analog, RF, and DRAM applications in ICs. The International Technology Roadmap for Semiconductors (ITRS) specifies continuing increase in capacitance density (> 7 fF/ m2), lower leakage current density (< 10 8 A/cm2), very low effective oxide thickness (EOT < 1 nm, for DRAM applications), and better capacitance density-voltage (C-V) linearity ( < 100 ppm/V2, for analog/RF applications). In addition, the maximum fabrication/processing temper-ature should not be greater than 400 0C, in order to be compatible with the thermal budget of back-end fabrication steps. Low dielectric constants of conventional SiO2 and Si3N4 capacitors limit the capacitance densities of these devices. Although scaling down of dielectric thickness increases the capacitance density, it results in large leakage current density and poor C-V linearity. In this work, the effects of high-k materials (Eu2O3, Gd2O3, TiO2) on the device performance of MIM capacitors are studied. The performance of multi-dielectric stack, and doped-dielectric stack devices are also investigated. The effects of anneal temperature, anneal ambient, anneal mode, and dielectric thickness on device performance are evaluated. C-V, current density-voltage (J-V), and reliability measurements are performed to benchmark the electrical performance, and this is correlated to the structural and material properties of the films through ellipsometry, scanning electron microscopy (SEM), X-ray diffraction (XRD), and X-ray photoelectron spectroscopy (XPS) measurements. High-performance MIM capacitors are fabricated by using (RF sputtered) Eu2O3 dielectric. The fabricated devices are subjected to different anneal conditions, to study their device performance. Forming gas (FG) and argon (Ar) annealed devices are shown to have higher capacitance densities (7 fF/ m2jF G), lower leakage current densities (3.2 10 8 A/cm2jAr at -1 V), and higher , compared to oxygen (O2) annealed de-vices ( 100kHz = 193 ppm/V2jO2). The electrical characterization results are correlated with the surface chemical states of the films through XPS measurements. The annealing ambient is shown to alter the surface chemical states, which, in turn, modulate the electrical characteristics. High-density MIM capacitors are fabricated by using (RF sputtered) Gd2O3, and Gd2O3-Eu2O3 stacked dielectrics. The fabricated Gd2O3 capacitors are also subjected to different anneal conditions, to study their device performance. Although Gd2O3 capacitors provide high capacitance density (15 fF/ m2), they suffer from high leakage current density, high , and poor reliability. Therefore, stacked dielectrics of Gd2O3 and Eu2O3 (Gd2O3/Eu2O3 and Eu2O3/Gd2O3) are fabricated to reduce leakage current density, improve , and improve reliability, with only a marginal reduction in capacitance density, compared to Gd2O3 capacitors. Density of defects and barrier/trap heights are extracted for the fabricated capacitors, and correlated with the device characteristics. High-performance MIM capacitors with bilayer dielectric stacks of (ALD-deposited) TiO2-ZrO2, and Si-doped ZrO2 are characterized. Devices with (ALD-deposited) TiO2/ ZrO2/TiO2 (TZT) and AlO-doped TZT stacks are also characterized. The influence of doping on the device performance is studied. The surface chemical states of the deposited films are analyzed by high-resolution XPS. The structural analysis of the samples is performed by XRD measurements, and this is correlated to the electrical characteristics of the devices. Reliability measurements are performed to study the effects of constant voltage and current stress on device performance. High capacitance density (> 45 fF/ m2), low leakage current density (< 5 10 8 A/cm2 at -1 V, for most devices), and sub-nm EOT are achieved. These parameters exceed the ITRS specifications for DRAM storage capacitors.