This thesis examines substrate noise coupling for NMOS transistors in heavily doped substrates. The study begins with the analysis of an NMOS transistor switching noise in a digital inverter at the device level. A resistive substrate network for the NMOS transistor is proposed and verified. Coupling between N+- P+ contacts is compared both qualitatively and quantitatively with simulations. The difference between the N-P and P-P coupling is in the cross-coupling parameter. A new N-P model, which requires only five parameters, is proposed by taking advantage of an existing P-P model combined with the concept of a virtual separation. This model has been validated up to 2GHz with Medici simulations. The virtual separation concept has been validated with 2D/3D simulations and measurements from test structures fabricated in a 0.35μm TSMC CMOS heavily doped process. This model is useful when transistor switching noise is the dominant source of substrate noise. Applications of the new N-P model are demonstrated with circuit simulations. / Graduation date: 2004

We present a new circuit design for adaptive offset cancellation in a fully differential 2.4 GHz CMOS direct conversion mixer. Our circuit structure is a modification of a Gilbert cell mixer in which offsets are cancelled by injecting cancellation currents into the legs of the mixer by dynamically varying the bias on the active loads. We present analysis and simulation results of our mixer with offsets present. Offsets create non-linearities in any circuit by differentially shifting the small-signal bias point of a matched pair; forcing once symmetrical transistors to operate in different bias regions and create second order distortion. We focus our design to minimize second order distortion while simultaneously canceling the large offsets found in direct conversion receivers. Simulation results for the mixer canceling a wide range of offsets are included. Our mixer has a gain of 6.4dB, an IIP3 of 17dBm and a noise figure of 17dB as simulated in a .5��m HP Mosis CMOS process. / Graduation date: 2002

Full integration of CMOS low noise amplifiers (LNA) presents a challenge for low cost CMOS receiver systems. A critical problem faced in the design of an RF CMOS LNA is the inaccurate high-frequency noise model of the MOSFET implemented in circuit simulators such as SPICE. Silicon-based monolithic inductors are another bottleneck in RF CMOS design due to their poor quality factor. In this thesis, a CMOS implementation of a fully-integrated differential LNA is presented. A small-signal noise circuit model that includes the two most important noise sources of the MOSFET at radio frequencies, channel thermal noise and induced gate current noise, is developed for CMOS LNA analysis and simulation. Various CMOS LNA architectures are investigated. The optimization techniques and design guidelines and procedures for an LC tuned CMOS LNA are also described. Analysis and modeling of silicon-based monolithic inductors and transformers are presented and it is shown that in fully-differential applications, a monolithic transformer occupies less die area and achieves a higher quality factor compared to two independent inductors with the same total effective inductance. It is also shown that monolithic transformers improve the common-mode rejection of the differential circuits. / Graduation date: 1999

In recent years, there has been an extensive effort to develop low-cost implementations of radio frequency integrated circuits for consumer applications. This thesis is a research effort in the design and implementation of integrated RF CMOS Power Amplifiers (PAs). A significant challenge in the implementation of RF CMOS ICs is the impact of device, package and passive element parasitics on circuit performance. Passive components are a critical part of any RF IC design, and a process optimized for digital circuits results in inductors and capacitors with very high parasitics. In this work, we have developed a compact model for inductors fabricated in a digital CMOS process. Measured results have been used to further refine the accuracy of the inductor model. This model has been used to predict the impact of inductor parasitics on the performance of RFICs, and is also simple enough to be included in a CAD tool for circuit optimization. We have also studied the operation of Class A, B and C power amplifiers and highlighted design issues which are specific to the implementation of integrated PAs. It is shown that inductor loss has the most critical impact on the performance of integrated PAs. A custom CAD tool, based on the simulated annealing algorithm, has been developed to optimize the performance of power amplifiers for maximum efficiency in the presence of package, device and passive element parasitics. This CAD tool simulates the process of load-pull to determine the optimum large-signal load impedance for the PA, and optimizes the matching network design based on the trade-off between the loss in the matching network and its impedance transformation properties. This trade-off is relevant in the case of high-loss matching networks only, as is the case in integrated RF CMOS ICs. This CAD tool has been used to optimize the efficiency of balanced 100mW CMOS PAs operating at 900MHz. Measured results validate the design and optimization process outlined in this work. It is demonstrated that in the design of RF CMOS ICs, significant benefits can be gained by incorporating parasitics into the design process by means of CAD optimization. The CAD tool developed is an effort towards achieving this goal. It is further proposed that CAD optimization is an essential part of the design of RF CMOS ICs in general, and with the development of improved package, device and passive element models, CAD optimization will replace the "tuning" of RF circuits and result in robust, fully-integrated implementations of RF circuits. / Graduation date: 1999

High-accuracy and high-speed CMOS track-and-hold (T/H) or sample-and-hold (S/H) circuits are an important part of the analog-to-digital interface. The switched-capacitor (SC) circuits usually contain one or more op-amps whose dc offset, finite gain, finite bandwidth have a big impact on the accuracy of the track-and-hold circuit. Basic correlated double sampling (CDS) scheme can reduce such effects, but the compensation that it provides may not be good enough for high-accuracy application. Also, the high-quality analog poly-poly capacitors used in most SC circuits are not available in a basic digital CMOS process. The MOSFET-only predictive track-and-hold circuit, discussed in this thesis, replaces the poly-poly capacitors with easily-available low-cost area-saving MOSFET capacitors biased in accumulation region. It also uses the predictive correlated double sampling (CDS) scheme, in which the op-amp predicts its output for the next clock period during the present clock period, so that the adjacent two output samples are nearly the same. The predictive operation results in more correlation between the unwanted signal and the signal that is subtracted during the double sampling, and hence can achieve offset and gain compensation over wider frequency range. Hence, this circuit is suitable for high-accuracy applications, while using only a basic digital process. / Graduation date: 1997

Previous work at Stanford University has demonstrated that inductance in the substrate connection is the principal problem underlying the coupling of digital switching noise into analog circuits. The low impedance substrate can be treated as a single node over a local area. Switching in the digital circuits produces current transients in the substrate. These transients are subsequently amplified in the analog portions of the overall mixed-mode circuit. Various guard rings and other techniques, including the use of new logic circuit families, have been proposed to suppress this noise. This work demonstrates that by using the capacitance of a forward biased guard ring(s), the substrate noise at a specific frequency(ies) can be reduced by resonating the guard ring capacitance with the substrate lead inductance to provide a very low substrate-to-ground impedance. In this manner, noise at particular frequencies, which are problematic to the analog circuit, can be suppressed. Tuning can be accomplished by varying the current in the forward-biased guard ring diodes. / Graduation date: 1995

Thesis (M.S.E.C.E.)--University of Delaware, 2007. / Principal faculty advisor: Michael W. Haney, Dept. of Electrical and Computer Engineering. Includes bibliographical references.

Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (leaves 158-164).

M.S. / Computer Science & Engineering / A Static Rule Checker for NMOS and CMOS VLSI Circuits is described. MOSSTAT makes a number of different static rule checks on a circuit. These checks help the user to detect and isolate errors such as improper network connectivity or invalid transistor sizes, and can be run interactively to allow for orderly execution each rule check. The results are stored in a data base. MOSSTAT provides a simple query language that allows the user to selectively retrieve this information from the data base. Transistors are classified according to their type and function. Logic gates are also classified according to their style. The results of these analyses are useful in isolating possible circuit design problems.