Evolutions in integrated circuit technology require the use of a high-frequency synchronous buck converter in order to achieve low cost, low profile, fast transient response and high power density. However, high frequency operation leads to increased power MOSFET switching losses. Optimization of the MOSFETs plays an important role in improving converter performance. This dissertation focuses on revealing the power loss mechanism of power MOSFETs and the relationship between power MOSFET structure and its power loss. The analytical device model, combined with circuit modeling, cannot reveal the relationship between device structure and its power loss due to the highly non-linear characteristics of power MOSFETs. A physically-based mixed device/circuit modeling approach is used to investigate the power losses of the MOSFETs under different operating conditions. The physically based device model, combined with SPICE-like circuit simulation, provides an expeditious and inexpensive way of evaluating and optimizing circuit and device concepts. Unlike analytical or other SPICE models of power MOSFETs, the numerical device model, relying little on approximations or simplifications, faithfully represents the behavior of realistic power MOSFETs. The impact of power MOSFET parameters on efficiency of synchronous buck converters, such as gate charge, on resistance, reverse recovery, is studied in detail in this thesis. The results provide a good indication on how to optimize power MOSFETs used in VRMs. The synchronous rectifier plays an important role in determining the performance of the synchronous buck converter. The reverse recovery of its body diode and the Cdv/dt induced false trigger-on are two major mechanisms that impact SyncFET's performance. This thesis gives a detailed analysis of the SyncFET operation mechanism and provides several techniques to reduce its body-diode influence and suppress its false Cdv/dt trigger-n. This thesis also investigates the influence of several circuit level parameters on the efficiency of the synchronous buck converter, such as input voltage, circuit parasitic inductance, and gate resistance to provide further optimization of synchronous buck converter design.