<p>Future radars require more flexible and faster radar signal processing chain than commercial radars of today. This means that the demands on the processors in a radar signal system, and the desire to be able to compute larger amount of data in lesser time, is constantly increasing. This thesis focuses on commercial micro-processors of today that can be used for Active Electronically Scanned Array Antenna (AESA) based radar, their physical size, power consumption and performance must to be taken into consideration. The evaluation is based on theoretical comparisons among some of the latest processors provided by PACT, PicoChip, Intrinsity, Clearspeed and IBM. The project also includes a benchmark made on PowerPC G5 from IBM, which shows the calculation time for different Fast Fourier Transforms (FFTs). The benchmark on the PowerPC G5 shows that it is up to 5 times faster than its predecessor PowerPC G4 when it comes to calculate FFTs, but it only consumes twice the power. This is due to the fact that PowerPC G5 has a double word length and almost twice the frequency. Even if this seems as a good result, all the PowerPC´s that are needed to reach the performance for an AESA radar chain would consume too much power. The thesis ends up with a discussion about the traditional architectures and the new multi-core architectures. The future belongs with almost certainty to some kind of multicore processor concept, because of its higher performance per watt. But the traditional single core processor is probably the best choice for more moderate-performance systems of today, if you as developer looking for a traditional way of programing processors.</p>

Future radars require more flexible and faster radar signal processing chain than commercial radars of today. This means that the demands on the processors in a radar signal system, and the desire to be able to compute larger amount of data in lesser time, is constantly increasing. This thesis focuses on commercial micro-processors of today that can be used for Active Electronically Scanned Array Antenna (AESA) based radar, their physical size, power consumption and performance must to be taken into consideration. The evaluation is based on theoretical comparisons among some of the latest processors provided by PACT, PicoChip, Intrinsity, Clearspeed and IBM. The project also includes a benchmark made on PowerPC G5 from IBM, which shows the calculation time for different Fast Fourier Transforms (FFTs). The benchmark on the PowerPC G5 shows that it is up to 5 times faster than its predecessor PowerPC G4 when it comes to calculate FFTs, but it only consumes twice the power. This is due to the fact that PowerPC G5 has a double word length and almost twice the frequency. Even if this seems as a good result, all the PowerPC´s that are needed to reach the performance for an AESA radar chain would consume too much power. The thesis ends up with a discussion about the traditional architectures and the new multi-core architectures. The future belongs with almost certainty to some kind of multicore processor concept, because of its higher performance per watt. But the traditional single core processor is probably the best choice for more moderate-performance systems of today, if you as developer looking for a traditional way of programing processors.