The number of application specific instruction set processors is rapidly increasing, because of increased demand for low power and small area designs. A lot of new instruction sets are born, but they are usually confidential. University of California in Berkeley took an opposite approach. The RISC-V instruction set is completely free. This master's thesis focuses on analysis of RISC-V instruction set and two programming languages used to model instruction sets and microarchitectures, CodAL and Chisel. Implementation of RISC-V base instruction set along with multiplication, division and 64-bit address space extensions and implementation of cycle accurate model of Rocket Core-like microarchitecture in CodAL are main goals of this master's thesis. The instruction set model is used to generate the C compiler and the cycle accurate model is used to generate RTL representation, all thanks to Codasip Studio. Generated compiler is compared against the one implemented manually and results are used for instruction set optimizations. RTL is synthesized to Artix 7 FPGA and compared to the Rocket Core synthesis.

This paper presents a novel implementation of an embedded Java microarchitecture for secure, realtime, and multi-threaded applications. Together with the support of modern features of object-oriented languages, such as exception handling, automatic garbage collection and interface types, a general-purpose platform is established which also fits for the agent concept. Especially, considering real-time issues, new techniques have been implemented in our Java microarchitecture, such as an integrated stack and thread management for fast context switching, concurrent garbage collection for real-time threads and autonomous control flows through preemptive round-robin scheduling.

<p>The risk of fracture is higher in adults with type 2 diabetes compared to controls without type 2 diabetes, despite normal or higher than normal bone mineral density (BMD). In addition to BMD, bone strength depends on other factors such as structural and material <em>bone qualities</em>, which are not accounted for in BMD measurements. The objective was to determine whether structural and material <em>bone qualities</em> are different in adults with type 2 diabetes compared to controls without type 2 diabetes. First, a cross-sectional study was undertaken using MRI to investigate distal radius trabecular bone microarchitecture, a structural <em>bone quality.</em> In women with type 2 diabetes, trabecular bone holes were larger compared to controls, which is important because greater trabecular bone hole size is related to reduced bone strength. Next, a two year prospective study was conducted with the participants involved in the cross-sectional study to determine whether changes in trabecular bone microarchitecture are different in women with type 2 diabetes compared to controls. There was a greater increase in the number of trabecular bone holes in women with type 2 diabetes compared to controls, which provides early evidence of trabecularization of cortical bone in women with type 2 diabetes. In the third study, quantitative backscattered electron imaging (qBEI) was used to derive bone mineralization density distribution (BMDD) outcomes for bone samples from adults with and without type 2 diabetes to compare material <em>bone quality. </em>There was evidence of elevated bone calcium concentration and reduced mineralization heterogeneity in bone samples from adults with type 2 diabetes compared to controls, which may contribute to bone brittleness. In summary, differences in structural and material <em>bone qualities </em>identified in this body of work provide explanations for elevated fracture risk in adults with type 2 diabetes.</p> / Doctor of Science (PhD)

Der Typ-2-Diabetes mellitus (T2DM) wird mit einem erhöhten Frakturrisiko in Verbindung gebracht, welches auf krankheitsspezifische Defizite in der Knochenmikrostruktur und -qualität zurückzuführen ist. Da die zugrundeliegenden Mechanismen unzureichend verstanden sind, kommen präklinische Modelle, welche die diabetische Knochenerkrankung nachbilden, zur Erforschung der Pathogenese zum Einsatz. Die TallyHo/JngJ (TH)-Maus ist ein polygenes Modell für spontan auftretenden T2DM und Adipositas, welches den T2DM im Jugendalter beim Menschen rekapituliert. Aufgrund der unvollständigen Penetranz des Phänotyps entwickeln ~25 % der männlichen TH-Mäuse nie eine Hyperglykämie und können somit als nicht-diabetische Kontrolltiere mit identischen genetischen Background verwendet werden. Im Rahmen dieser Arbeit verwendeten wir männliche diabetische TH-Mäuse im Alter von zwölf Wochen für eine umfassende Charakterisierung des metabolischen und skelettalen Phänotyps und verglichen sie entweder mit altersgleichen nicht-diabetischen TH-Kontrollen oder mit den empfohlenen SWR/J-Kontrollen. Männliche TH-Mäuse mit T2DM zeigten eine Hyperglykämie und ein höheres Gewicht zusammen mit einer gestörten Glukosetoleranz und Insulinresistenz im Vergleich zu SWR/J und nicht-diabetischen TH-Kontrollen. Anhand der Mikro-Computertomographie (μCT) konnten festgestellt werden, dass TH-Mäuse mit T2DM ein erhöhtes kortikales Knochenvolumen und eine gesteigerte kortikale Knochendicke am Femur aufwiesen, während sie im Vergleich zu den SWR/J-Kontrollen einen trabekulären Knochenverlust sowohl im Femur als auch im Wirbelkörper zeigten. Trotz des trabekulären Knochenverlusts bei TH-Mäusen konnten wir keine Unterschiede im Bezug zum Knochenumbau feststellen, welcher anhand von Histomorphometrie und Serummarker zwischen diabetischen und nicht-diabetischen TH-Mäusen bestimmt wurde. Im Vergleich zu den SWR/J-Mäusen waren die Serum-Konzentrationen von Knochenumbaumarker P1NP und TRAcP5b bei TH-Mäusen niedriger, was darauf hindeutet, dass der SWR/J-Stamm per se einen höheren Knochenumsatz aufweisen könnte. Die biomechanischen Eigenschaften wurden mit einem 3-Punkt-Biegetest am Femur und einem Kompressionstest an der Wirbelsäule (L4) geprüft. Während es keine Unterschiede in der Knochenstärke des Femurs zwischen allen drei Gruppen gab, zeigte der Kompressionstest, dass der L4-Wirbelkörper von SWR/J-Mäusen im Vergleich zu den beiden Untergruppen der TH-Mäuse stärker waren. Im Rahmen der Osteozytencharakterisierung wurde eine niedrigere Anzahl von Osteozyten und ihren Dendriten bei TH-Mäusen mit T2DM durch Silbernitratfärbung im trabekulären Knochen des Femurs festgestellt. Die dreidimensionale Auswertung des ultrahochauflösenden μCT zeigte ein höheres Lakunenvolumen und eine höhere Lakunendichte bei SWR/J-Tieren im Vergleich zu beiden TH-Untergruppen im trabekulären und kortikalen Knochen des Femurs und des Wirbelkörpers. Weiterhin wurden Veränderungen in der Morphologie der Lakunen beobachtet wurden, wobei die Osteozyten bei TH-Mäusen mit T2DM im Vergleich zu SWR/J weniger kugelförmig, dafür aber gestreckter waren, was darauf hindeutet, dass die Form der Osteozyten ein Kompensationsmechanismus für die geringe Knochenmasse sein könnte. Eine hochkalorische Ernährung ist die Hauptursache für das Fortschreiten von Adipositas und T2DM. Daher ist eine diätetische Intervention, wie z. B. eine Kalorienrestriktion und eine Änderung der Ernährungszusammensetzung, ein wichtiger Behandlungsansatz zur Verbesserung der T2DM-Symptomatik. Es konnte gezeigt werden, dass eine ballaststoffreiche Ernährung die Hyperglykämie verbessert, die Hyperinsulinämie abschwächt und Entzündungen im Zusammenhang mit T2DM reduziert. Der Einfluss einer ballaststoffreiche Ernährung auf die Knochengesundheit im T2DM Kontext wurde jedoch bislang nicht erforscht. In unserer Studie verwendeten wir TH-Mäuse mit T2DM, die entweder mit einer Kontrolldiät oder einer ballaststoffreichen Diät gefüttert wurden. Wir konnten bestätigen, dass eine ballaststoffreiche Ernährung die T2DM-Symptome bei diabetischen TH-Mäusen verbessert. Während die ballaststoffreiche Ernährung keinen Effekt auf die kortikale oder trabekuläre Knochenstruktur im Femur bei diabetischen TH-Mäusen hatte, konnten wir eine geringere trabekuläre Knochenmasse in den Wirbelkörpern beobachteten. Eine ballaststoffreiche Ernährung hatte in beiden Gruppen keinen Einfluss auf die biomechanischen Eigenschaften von Oberschenkel- und Wirbelknochen. Anhand histomorphometrischer Analysen konnten wir eine Tendenz zur verstärkten Knochenformation nachweisen, jedoch war die Expression von Genen, die mit der Knochenbildung und dem WNT-Signalweg zusammenhängen, nicht verändert. Zusammenfassend zeigt diese Doktorarbeit die wesentlichen Charakteristika und potenziellen Einschränkungen der TALLYHO/JngJ- und SWR/J-Mausmodelle bei der Untersuchung von T2DM und dessen Auswirkungen auf die Knochengesundheit auf. Da sich die Knochenmikroarchitektur zwischen diabetischen und nichtdiabetischen TH-Mäusen nicht unterschied, ist diese Mauslinie kein ideales Modell zur Untersuchung diabetischer Knochenerkrankungen. Dennoch verbesserte eine ballaststoffreiche Ernährung den T2DM an sich, was bestätigt, dass TALLYHO/JngJ-Mäuse ein geeignetes präklinisches Modell sind, um die dem T2DM zugrundeliegenden Mechanismen abseits des Knochengewebes zu untersuchen. Diese Ergebnisse verdeutlichen uns die Notwendigkeit der Erforschung weiterer repräsentativerer Tiermodelle, um unser Verständnis von T2DM-bedingten Knochenerkrankungen zu verbessern.

Network on Chips[1][2][3][4] are critical elements of modern System on Chip(SoC) as well as Chip Multiprocessor(CMP)designs. Network on Chips (NoCs) help manage high complexity of designing large chips by decoupling computation from communication. SoCs and CMPs have a multiplicity of communicating entities like programmable processing elements, hardware acceleration engines, memory blocks as well as off-chip interfaces. With power having become a serious design constraint[5], there is a great need for designing NoC which meets the target communication requirements, while minimizing power using all the tricks available at the architecture, microarchitecture and circuit levels of the de-sign. This thesis presents a holistic, QoS based, power optimal design solution of a NoC inside a CMP taking into account link microarchitecture and processor tile configurations. Guaranteeing QoS by NoCs involves guaranteeing bandwidth and throughput for connections and deterministic latencies in communication paths. Label Switching based Network-on-Chip(LS-NoC) uses a centralized LS-NoC Management framework that engineers traffic into QoS guaranteed routes. LS-NoC uses label switching, enables band-width reservation, allows physical link sharing and leverages advantages of both packet and circuit switching techniques. A flow identification algorithm takes into account band-width available in individual links to establish QoS guaranteed routes. LS-NoC caters to the requirements of streaming applications where communication channels are fixed over the lifetime of the application. The proposed NoC framework inherently supports heterogeneous and ad-hoc SoC designs. A multicast, broadcast capable label switched router for the LS-NoC has been de-signed, verified, synthesized, placed and routed and timing analyzed. A 5 port, 256 bit data bus, 4 bit label router occupies 0.431 mm2 in 130nm and delivers peak band-width of80Gbits/s per link at312.5MHz. LS Router is estimated to consume 43.08 mW. Bandwidth and latency guarantees of LS-NoC have been demonstrated on streaming applications like Hiper LAN/2 and Object Recognition Processor, Constant Bit Rate traffic patterns and video decoder traffic representing Variable Bit Rate traffic. LS-NoC was found to have a competitive figure of merit with state-of-the-art NoCs providing QoS. We envision the use of LS-NoC in general purpose CMPs where applications demand deterministic latencies and hard bandwidth requirements. Design variables for interconnect exploration include wire width, wire spacing, repeater size and spacing, degree of pipelining, supply, threshold voltage, activity and coupling factors. An optimal link configuration in terms of number of pipeline stages for a given length of link and desired operating frequency is arrived at. Optimal configurations of all links in the NoC are identified and a power-performance optimal NoC is presented. We presents a latency, power and performance trade-off study of NoCs using link microarchitecture exploration. The design and implementation of a framework for such a design space exploration study is also presented. We present the trade-off study on NoCs by varying microarchitectural(e.g. pipelining) and circuit level(e.g. frequency and voltage) parameters. A System-C based NoC exploration framework is used to explore impacts of various architectural and microarchitectural level parameters of NoC elements on power and performance of the NoC. The framework enables the designer to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. Latency, power and throughput results using this framework to study a 4x4 CMP are presented. The framework is used to study NoC designs of a CMP using different classes of parallel computing benchmarks[6]. One of the key findings is that the average latency of a link can be reduced by increasing pipeline depth to a certain extent, as it enables link operation at higher link frequencies. Abstract There exists an optimum degree of pipelining which minimizes the energy-delay product of the link. In a 2D Torus when the longest link is pipelined by 4 stages at which point least latency(1.56 times minimum) is achieved and power(40% of max) and throughput (64%of max) are nominal. Using frequency scaling experiments, power variations of up to40%,26.6% and24% can be seen in 2D Torus, Reduced 2D Torus and Tree based NoC between various pipeline configurations to achieve same frequency at constant voltages. Also in some cases, we find that switching to a higher pipelining configuration can actually help reduce power as the links can be designed with smaller repeaters. We also find that the overall performance of the ICNs is determined by the lengths of the links needed to support the communication patterns. Thus the mesh seems to perform the best amongst the three topologies(Mesh, Torus and Folded Torus) considered in case studies. The effects of communication overheads on performance, power and energy of a multiprocessor chip using L1,L2 cache sizes as primary exploration parameters using accurate interconnect, processor, on-chip and off-chip memory modelling are presented. On-chip and off-chip communication times have significant impact on execution time and the energy efficiency of CMPs. Large cache simply larger tile area that result in longer inter-tile communication link lengths and latencies, thus adversely impacting communication time. Smaller caches potentially have higher number of misses and frequent of off-tile communication. Energy efficient tile design is a configuration exploration and trade-off study using different cache sizes and tile areas to identify a power-performance optimal configuration for the CMP. Trade-offs are explored using a detailed, cycle accurate, multicore simulation frame-work which includes superscalar processor cores, cache coherent memory hierarchies, on-chip point-to-point communication networks and detailed interconnect model including pipelining and latency. Sapphire, a detailed multiprocessor execution environment integrating SESC, Ruby and DRAM Sim was used to run applications from the Splash2 benchmark(64KpointFFT).Link latencies are estimated for a16 core CMP simulation on Sapphire. Each tile has a single processor, L1 and L2 caches and a router. Different sizesofL1 andL2lead to different tile clock speeds, tile miss rates and tile area and hence interconnect latency. Simulations across various L1, L2 sizes indicate that the tile configuration that maximizes energy efficiency is related to minimizing communication time. Experiments also indicate different optimal tile configurations for performance, energy and energy efficiency. Clustered interconnection network, communication aware cache bank mapping and thread mapping to physical cores are also explored as potential energy saving solutions. Results indicate that ignoring link latencies can lead to large errors in estimates of program completion times, of up to 17%. Performance optimal configurations are achieved at lower L1 caches and at moderateL2 cache sizes due to higher operating frequencies and smaller link lengths and comparatively lesser communication. Using minimal L1 cache size to operate at the highest frequency may not always be the performance-power optimal choice. Larger L1 sizes, despite a drop in frequency, offer a energy advantage due to lesser communication due to misses. Clustered tile placement experiments for FFT show considerable performance per watt improvement (1.2%). Remapping most accessed L2 banks by a process in the same core or neighbouring cores after communication traffic analysis offers power and performance advantages. Remapped processes and banks in clustered tile placement show a performance per watt improvement of5.25% and energy reductionof2.53%. This suggests that processors could execute a program in multiple modes, for example, minimum energy, maximum performance.

Master‘s thesis reviews the characteristics of the AVR32 architecture, AVR32UC microarchitecture, and especially AT32UC3A0512 microcontroller. This microcontroller is mounted on the board EVK1100, which is used for debugging applications. The entire analysis is focused on the ability to process audio signals on this board. For the board is created AD/DA interface and its control library. Follows necessary description of used DSP-lib library. The last part is a description of the theory and implementation of two sound effects and implementation of operating system FreeRTOS.