Integrated Circuit (IC) designs are increasingly moving towards Intellectual Property (IP) reuse for various targeted products and market segments. Therefore, there is a need to share and synergize internal bus architectures to enable the reuse of IP blocks for various ASIC and SoC applications. Due to the different market segments of various ASICs and SoCs, design teams and architects have opted to use customized internal bus architectures to suit the respective targeted features for their market segments. As a result, many ASIC and SoC companies that produce microprocessors for computers, microcontrollers for consumer electronics as well as memory and I/O controller chipsets have opted to use different internal interfaces, designs and IPs for the different products that they sell. A modular and configurable bus architecture that is flexible and capable of supporting IPs from various ASICs and SoCs would serve to solve many of the problems relating to IP reuse for various applications from a front end design perspective. There are several approaches to resolve this, for example, using a standard existing open source bus, a new all-encompassing bus that covers the needs of the majority of designs and a customization of a particular bus level such as the interface layer, where part of the bus features are fixed and the rest of them are determined by individual design groups. This research covers the analysis of existing bus architectures in industry and considers the various options for bus architecture optimization for design modularity, bus performance and IP reuse with existing technology. The architecture definition, design, logic simulation and performance comparisons of the proposed bus architecture on industry standard RTL design and validation tools was then conducted.