Not available / text

Benchmarks set standards for innovation in computer architecture research and industry product development. Consequently, it is of paramount importance that the benchmarks used in computer architecture research and development are representative of real-world applications. However, composing such representative workloads poses practical challenges to application analysis teams and benchmark developers - (1) Benchmarks that are standardized are open-source whereas applications of interest are typically proprietary, (2) Benchmarks are rigid, measure single-point performance, and only represent a sample of the application behavior space (3) Benchmark suites take several years to develop, but applications evolve at a faster rate, and (4) Benchmarks geared towards temperature and power characterization are difficult to develop and standardize. The objective of this dissertation is to develop an adaptive benchmark generation strategy to construct synthetic benchmarks to address these benchmarking challenges. We propose an approach for automatically distilling key hardware-independent performance attributes of a proprietary workload and capture them into a miniature synthetic benchmark clone. The advantage of the benchmark clone is that it hides the functional meaning of the code, but exhibits similar performance and power characteristics as the target application across a wide range of microarchitecture configurations. Moreover, the dynamic instruction count of the synthetic benchmark clone is substantially shorter than the proprietary application, greatly reducing overall simulation time -- for the SPEC CPU 2000 suite, the simulation time reduction is over five orders of magnitude compared to the entire benchmark execution. We develop an adaptive benchmark generation strategy that trades off accuracy to provide the flexibility to easily alter program characteristics. The parameterization of workload metrics makes it possible to succinctly describe an application's behavior using a limited number of fundamental program characteristics. This provides the ability to alter workload characteristics and construct scalable benchmarks that allows researchers to explore a wider range of the application behavior space, conduct program behavior studies, and model emerging workloads. The parameterized workload model is the foundation for automatically constructing power and temperature oriented synthetic workloads. We show that machine learning algorithms can be effectively used to search the application behavior space to automatically construct benchmarks for evaluating the power and temperature characteristics of a computer architecture design. The need for a scientific approach to construct synthetic benchmarks, to complement application benchmarks, has long been recognized by the computer architecture research community, and this dissertation work is a significant step towards achieving that goal.

Procedures for designing and writing a CPU self-test program are developed for microprocessors in general. Specific examples of these procedures are then provided for both a simple example processor and for the Intel 8080; fault coverage statistics are provided for the 8080 test. The self-test methodology overlaps the tests for different elements within the CPU in order to attain a very quick test suitable for periodic background testing. Generalized fault classes are defined for the CPU and methods for sensitizing and detecting these faults are detailed. General procedures and hardware requirements for self-testing the entire microcomputer system within its operating environment are discussed. Fault simulation techniques are also discussed; simulation provides feedback on the effectiveness of a self-test and allows the test to be improved for better coverage and faster execution. / Master of Science

Not available / text

Yau Po Chung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references (leaves 91-92). / Abstract also in Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Background --- p.3 / Chapter 2.1 --- Temporal Theories --- p.3 / Chapter 2.2 --- Related Works --- p.4 / Chapter 2.2.1 --- Consistency and Satisfiability of Timing Specifications --- p.4 / Chapter 2.2.2 --- Symbolic Constraint Satisfaction --- p.5 / Chapter 3 --- Previous Developed Work --- p.7 / Chapter 3.1 --- Previous Problem Domain --- p.7 / Chapter 3.1.1 --- Basics of MC68000 Read Cycle --- p.7 / Chapter 3.2 --- Knowledge-based System Structure --- p.9 / Chapter 3.3 --- Diagnostic Reasoning Mechanisms --- p.10 / Chapter 3.4 --- Time Range Approach --- p.11 / Chapter 3.4.1 --- Time Range Representation --- p.11 / Chapter 3.4.2 --- Constraint Satisfaction of Time Ranges --- p.12 / Chapter 3.4.3 --- Constraint Propagation of Time Ranges --- p.13 / Chapter 3.5 --- Fuzzy Time Point Approach --- p.14 / Chapter 3.5.1 --- Fuzzy Time Point Models --- p.14 / Chapter 3.5.2 --- Definition of Fuzzy Time Points --- p.15 / Chapter 3.5.3 --- Constraint Propagation of Fuzzy Time Points --- p.17 / Chapter 3.5.4 --- Constraint Satisfaction of Fuzzy Time Points --- p.18 / Chapter 4 --- The Proposed Segmented Time Range Approach --- p.20 / Chapter 4.1 --- Introduction --- p.20 / Chapter 4.2 --- The Insufficiency of The Existing Time Range Approach --- p.22 / Chapter 4.3 --- Segmented Time Range Approach --- p.23 / Chapter 4.3.1 --- The Representation --- p.23 / Chapter 4.3.2 --- Constraint Propagation and Satisfaction --- p.25 / Chapter 4.3.3 --- Contributions --- p.25 / Chapter 4.3.4 --- Limitations --- p.29 / Chapter 4.4 --- Conclusion --- p.30 / Chapter 5 --- New Problem Domain and Our New System --- p.31 / Chapter 5.1 --- Introduction --- p.31 / Chapter 5.2 --- Pentium-SRAM Interfacing Problem --- p.31 / Chapter 5.2.1 --- Asynchronous SRAM Solution --- p.32 / Chapter 5.2.2 --- Synchronous SRAM Solution --- p.33 / Chapter 5.3 --- The Knowledge Base --- p.35 / Chapter 5.4 --- Characteristics of Our New System --- p.35 / Chapter 6 --- Burst Read Cycle --- p.37 / Chapter 6.1 --- Introduction --- p.37 / Chapter 6.2 --- Asynchronous SRAM Solution --- p.37 / Chapter 6.2.1 --- Implementation --- p.39 / Chapter 6.2.2 --- Implementation Results --- p.45 / Chapter 6.3 --- Synchronous SRAM Solution --- p.48 / Chapter 6.3.1 --- Implementation --- p.49 / Chapter 6.3.2 --- Implementation Results --- p.56 / Chapter 6.4 --- Conclusion --- p.58 / Chapter 7 --- Burst Write Cycle --- p.60 / Chapter 7.1 --- Introduction --- p.60 / Chapter 7.2 --- Asynchronous SRAM Solution --- p.60 / Chapter 7.2.1 --- Implementation --- p.61 / Chapter 7.2.2 --- Implementation Results --- p.67 / Chapter 7.3 --- Synchronous SRAM Solution --- p.71 / Chapter 7.3.1 --- Implementation --- p.71 / Chapter 7.3.2 --- Implementation Results --- p.79 / Chapter 7.4 --- Conclusion --- p.82 / Chapter 8 --- Conclusion --- p.83 / Chapter 8.1 --- Summary of Achievements --- p.83 / Chapter 8.2 --- Future Development --- p.86 / Appendix Some Characteristics of Our New System --- p.89 / Bibliography --- p.91

Thesis (MScEng)--University of Stellenbosch, 2002. / ENGLISH ABSTRACT: For space designs, just as for terrestrial applications, the appetite for more computing power is virtually insatiable. Further, like portable applications, space use implies severe power constraints. Among currently available commercial processors, the PowerPC family ranks high in Million Instructions Per Second (MIPS) per watt, but its suitability for space applications outside low-earth orbits (LEOs) may be limited by the radiation environment, particularly single ev nt effects (SEE). This thesis covers the feasibility of using the PowerPC 603e™ processor for LEO satellite applications. The PowerPC architecture is well established with an excellent roadmap, which makes for a baseline microprocessor with long-term availability and excellent software support. The evaluation board design leverages Commercial Off-The-Shelf (COTS) technologies, allowing early integration and test. It provides a clear path to upgrades and provides a high performance platform to suit multiple missions. / AFRIKAANSE OPSOMMING: Die soeke na rekenaars met hoer werkverrigting sal nooit ophou rue. Dit geld vir beide rekenaars op aarde as satelliet aanboord rekenaars. Rekenaars vir ruimte gebruik word ook streng drywingsbeperkings opgele. Die PowerPC familie vergelyk baie goed met ander verwerkers, maar hul bruikbaarheid vir ruimte toepassings kan dalk beperk word tot lae wentelbane waar die ruimte radiasie omgewing meer toeganklik is. Die skrywe behandel die bruikbaarheid van die PowerPC 603e verwerker vir lae wentelbaan satelliet gebruik. Die welgestelde argitektuur, bekombaarheid en uitstekende sagte- _ ware ondersteuning verseker 'n standvastige fondasie. Kornmersiele komponente het voorkeur geniet in die hardeware ontwerp wat spoedige ontwikkeling sowel as aanpasbaarheid verseker. Die ontwerp bied 'n hoe werkverrigting en maklik opgradeerbare oplossing vir 'n groot verskeidenheid gebruike.

Thesis (MScEng)--University of Stellenbosch, 2002. / ENGLISH ABSTRACT: After successful use of a DSP processor onboard the SUNSAT satellite, the need arose for a faster floating-point processor. A list of possible processors was generated from various selection criteria. Two suitable DSP processors were chosen, and because no radiation information was available for one of them, the decision was made to perform radiation tests on it. The procedures used to test the processor are described in detail so the same methods can be used for future radiation tests. An error detection and correction circuit was implemented to check and correct upsets in the on-chip memory of the DSP processor. This ensures that the processor code and data stays intact. / AFRIKAANSE OPSOMMING: Na suksesvolle gebruik van 'n DSP verwerker aanboord die SUNSAT satelliet het die behoefte ontstaan vir 'n vinniger wissel-punt verwerker. 'n Lys van moontlike verwerkers is opgestel met die hulp van verskeie seleksie kriteria. Twee geskikte DSP verwerkers is gekies, en omdat geen radiasie informasie vir die een beskikbaar was nie, is besluit om radiasie toetse op hom te doen. Die prosedures gebruik om die verwerker te toets word deeglik beskryf sodat dieselfde metodes in die toekom gebruik kan word. 'n Fout deteksie en korreksie baan is geimplementeer om foute in die aanboord geheue van die DSP verwerker op te spoor en te korrigeer. Dit verseker dat die verwerker se kode en data intak bly.