Miniaturization and functionality have always governed advances in electronic system technology. To truly achieve the goal of a multi mega-functional system, advances must be made not just at the IC level, but at the system level too. This concept of tighter integration at the system level is called System-on-Package (SOP). While SOP has a wide range of applications, this work targets the mobile application space. The main driver in the mobile application space is package profile. Reduction in thickness is very critical for enabling next-generation ultra-high density mobile products. In order to pack more functionality into a smaller volume, it is absolutely imperative that package profiles are reduced. The NEMI roadmap projects that the package profile should be reduced to 200µm from the current 500µm by 2014. This work attempts to demonstrate the feasibility of ultra-thin substrates (<200µm) using a new advanced material system tailored for high-frequency mobile applications. The main barriers to adoption of thin substrates include processing challenges, concerns about via and through hole reliability and warpage. Each of these factors is studied and a full-fledged test vehicle built to demonstrate the reliability of thin substrates using the advanced low-loss RXP-4/RXP-1 material system. Finite element models are developed to provide an understanding of the factors that affect the reliability of these substrates. Finally, IC assembly is demonstrated on these substrates.

Current board technologies are inherently performance-limited (FR-4) or cost-prohibitive (Al2O3/AlN). Next-generation high-density packaging applications would necessitate a new base substrate material to achieve ultra-fine pitch solder-joint reliability and multiple layers of fine-line wiring at low cost. The NEMI 2000 roadmap defines the need for 4-8 layers of 5-10 m wiring for future system boards. The 2003 ITRS roadmap calls for organic substrates with less than 100-m area-array pitch in the package or board by year 2010. Solder-joint reliability at such fine-pitch is a matter of concern for the industry. Use of underfills reduces thermal stresses but increases cost and, in addition, their dispensing becomes increasingly more complicated with the shorter gaps required for future interconnects. Therefore, there is a pronounced need to evaluate board materials with CTE close to that of Si for reliable flip-chip on board without underfill. Recently, a novel manufacturing process (using polymeric precursor) has been demonstrated to yield boards that have the advantages of organic boards in terms of large-area processability and machinability at potentially low-cost while retaining the high stiffness (~250 GPa) and Si-matched CTE (~2.5 ppm/㩠of ceramics. This work reports the evaluation of novel SiC-based ceramic composite board material for ultra-fine pitch solder-joint reliability without underfill and multilayer support. FE models were generated to model the behavior of flip-chips assembled without underfill and subjected to accelerated thermal cycling. These models were used to calculate solder-joint strains which have a strong direct influence on fatigue life of the solder. Multilayer structures were also simulated for thermal shock testing so as to assess via strains for microvia reliability. Via-pad misregistration was derived from the models and compared for different boards. Experiments were done to assemble flip-chips on boards without underfill followed by thermal shock testing so as to get the number of cycles to failure. To assess microvia reliability, 2 layer structures containing vias of different diameters were fabricated and subjected to thermal cycling. Via-pad misalignment was also studied experimentally. Modeling and experimental results were corroborated so as to evaluate thermomechanical suitability of C-SiC for high-density packaging requirements.

Recent advances in the miniaturization, functionality, and integration of integrated circuits and packages, such as the system-on-package (SOP) methodology, require increasing use of microvias that generates vertical signal paths in a high-density multilayer substrate. A scanning projection excimer laser system has been utilized to fabricate the microvias. In this thesis, a novel technique implementing statistical experimental design and neural networks (NNs) is used to characterize and model the excimer laser ablation process for microvia formation. Vias with diameters from 10 50 micrometer have been ablated in DuPont Kapton(r) E polyimide using an Anvik HexScan(tm) 2150 SXE pulsed excimer laser operating at 308 nm. Accurate NN models, developed from experimental data, are obtained for microvia responses, including ablated thickness, via diameter, wall angle, and resistance. Subsequent to modeling, NNs and genetic algorithms (GAs) are utilized to generate optimal process recipes for the laser tool. Such recipes can be used to produce desired microvia responses, including open vias, specific diameter, steep wall angle, and low resistance. With continuing advancement in the use of excimer laser systems in microsystems packaging has come an increasing need to offset capital equipment investment and lower equipment downtime. In this thesis, an automated in-line failure diagnosis system using NNs and Dempster-Shafer (D-S) theory is implemented. For the sake of comparison, an adaptive neuro-fuzzy approach is applied to achieve the same objective. Both the D-S theory and neuro-fuzzy logic are used to develop an automated inference system to specifically identify failures. Successful results in failure detection and diagnosis are obtained from the two approaches. The result of this investigation will benefit both engineering and management. Engineers will benefit from high yield, reliable production, and low equipment down-time. Business people, on the other hand, will benefit from cost-savings resulting from more production-worthy (i.e., lower maintenance) laser ablation equipment.