Over the past couple decades, the capabilities of battery-powered electronics has expanded dramatically. What started out as large bulky 2-way radios, wristwatches, and simple pacemakers, has evolved into pocket sized smart-phones, digital cameras, person digital assistants, and implantable biomedical chips that can restore hearing and prevent heart attacks. With this increase in complexity comes an increase in the amount of processing, which runs on a limited energy source such as a battery or scavenged energy. It is therefore desirable to make the hardware as energy efficient as possible. Many battery-powered systems require digital signal processing, which often makes up a large portion of the total energy consumption. The digital signal processing of a battery-powered system is therefore a good target for power reduction techniques. One method of reducing the power consumption of digital signal processing is to operate the circuit in the subthreshold region, where the supply voltage is lower than the threshold voltage of the transistors. Subthreshold operation greatly reduces the power and energy consumption, but also decreases the maximum operating frequency. Many digital signal processing applications have real-time throughput requirements, so various architectural level techniques, such as pipelining and parallelism, must be used in order to achieve the required performance. This thesis investigates the use of parallelization and subthreshold operation to lower the power consumption of digital signal processing applications, while still meeting throughput requirements. Using an off the shelf fast fourier transform architecture, it will be shown that through parallelization and subthreshold operation, a 70% reduction in power consumption can be achieved, all while matching the performance of a nominal voltage single core architecture. Even better results can be obtained when an architecture is specifically designed for subthreshold operation. A novel Discrete Wavelet Transform architecture is presented that is designed to eliminate the need for memory banks, and a power reduction of 26x is achieved compared to a reference nominal voltage architecture that uses memory banks. Issues such as serial to parallel data distribution, dynamic throughput scaling, and memory usage are also explored in this thesis. Finally, voltage scaling greatly increases the design space, so power and timing analysis can be very slow due long SPICE simulation times. A simulation framework is presented that can characterize subthreshold circuits accurately using only fast gate level design automation tools. / Master of Science

Water infrastructure systems worldwide use large amounts of energy to operate. Energy efficiency efforts are relevant because even relatively small gains in efficiency have the potential to bring significant benefits to these utilities in terms of financial savings and enhanced sustainability and resiliency. In order to achieve higher efficiency levels, energy usage must be measured and controlled. A common tool used to measure energy efficiency in water utilities and perform comparisons between utilities is metric benchmarking. Energy benchmarking scores are intended to measure how efficient water systems are among their peers, in a simple and accurate fashion. Although many different benchmarking methods are currently used, we chose to use the segregated benchmarking scores proposed by Carlson on his research report from 2007 (Carlson, 2007). The research objective is to improve these production energy use and treatment energy use benchmarking scores by analyzing the system's particular characteristics that might skew the results, such as topology, water loss and raw water quality. We propose that benchmarking metrics should be always used within a particular context for each specific utility being analyzed. A complementary score (Thermodynamic Score) was developed to provide context on how energy efficient is the utility not only compared with other utilities, but also compared with the potential maximum efficiency the utility can reach itself. We analyzed eight utilities from Virginia to obtain production and treatment energy use benchmarking scores and also thermodynamic scores using the minimum required energy approach. Benchmarking scores were skewed in 50% of the studied utilities. This means that benchmarking scores should never be used as a black box. The thermodynamic score proved to be useful for measurement of energy efficiency of a water utility on its production phase. In addition, some utilities can detect significant financial saving opportunities using the minimum required energy analysis for production operations. / Master of Science

The CMS Tracker is an all silicon detector and it is the biggest of its kind to be built. The system consists of over 15,000 individual detector modules giving rise to readout through almost 107 channels. The data generated by the Tracker system is close to 650 MB at 40 MHz. This has created a challenge for the CMS collaborators in terms of data storage for analysis. To store only the interesting physics data the readout rate has to be reduced to 100 Hz where the data has to be ltered through a monitoring system for quality checks. The Tracker being the closest part of the detector to the interaction point of the CMS creates yet another challenge that needs the data quality monitoring system. As it operates in a very hostile environment the silicon detectors used to detect the particles will be degraded. It is very important to monitor the changes in the sensor behaviour with time so that to calibrate the sensors to compensate for the erroneous readings. This thesis discusses the development of a monitoring system that will enable the checking of data generated by the tracker to address the issues discussed above. The system has two parts, one dealing with the data used to monitor the Tracker and a second one that deals with statistical methods used to check the quality of the data.

Opportunistic spectrum reuse is a promising solution to the two main causes of spectrum scarcity: most of the radio frequency (RF) bands are allocated by static licensing, and many of them are underutilized. Frequency spectrum can be more efficiently utilized by allowing communication systems to find out unoccupied spectrum and to use it harmlessly to the licensed users. Reliable sensing of these spectral opportunities is perhaps the most essential element of this technology. Despite significant work on spectrum sensing, further performance improvement is needed to approach its full potential. In this dissertation, wireless spectrum sensing networks (WSSNs) are investigated for reliable detection of the primary (licensed) users, that enables efficient spectrum utilization and minimal power consumption in communications. Reliable spectrum sensing is studied in depth in two parts: a single sensor algorithm and then cooperative sensing are proposed based on a spectral covariance sensing (SCS). The first novel contribution uses different statistical correlations of the received signal and noise in the frequency domain. This detector is analyzed theoretically and verified through realistic simulations using actual digital television signals captured in the US. The proposed SCS detector achieves significant improvement over the existing solutions in terms of sensitivity and also robustness to noise uncertainty. Second, SCS is extended to a distributed WSSN architecture to allow cooperation between 2 or more sensors. Theoretical limits of cooperative white space sensing under correlated shadowing are investigated. We analyze the probability of a false alarm when each node in the WSSN detects the white space using the SCS detection and the base station combines individual results to make the final decision. The detection performance compared with that of the cooperative energy detector is improved and fewer sensor nodes are needed to achieve the same sensitivity. Third, we propose a low power source coding and modulation scheme for power efficient communication between the sensor nodes in WSSN. Complete analysis shows that the proposed scheme not only minimizes total power consumption in the network but also improves bit error rate (BER). / text

In an attempt to describe how patterns emerge in biological systems, Alan Turing proposed a mathematical model encapsulating the properties of such processes. It details a partial differential equation governing the dynamics of two or more substances, called morphogens, reacting and diffusing in a specific manner, in turn generating what has now come to be denoted as Turing patterns. In recent years, evidence has accumulated to support Turing's claim and it has been proposed that it is responsible for the dynamical characteristics of phenomena such as skin pigmentation and branching of lungs in vertebrates. The aim of this paper is to study how the choice of model parameters and reaction kinetics influence the nature of patterns generated, as well as explore how boundary control can be employed to generate pre-defined patterns and the efficiency of this procedure. To simulate the patterns, the differential equation is solved in Python by means of a spectral method using discretized space and time domains. The model parameters were then studied to try to gain insight in their effects on the patterns yielded. The boundary control was implemented in MATLAB using a difference method. The metric used for efficiency was taken to be the energy expenditure of the boundary cells. The complex dynamics of the studied systems make it difficult to draw valuable conclusions on the influence of the parameters, but the results support the expected characteristics of the models used. The efficiency of the pattern generation is deemed to be closely related to the amount of boundary control utilized.

China is the world’s largest producer and consumer of household appliances, lighting and commercial equipment. China first adopted Minimum Energy Performance Standards (MEPS) in 1989. By 2013, China has developed and implemented 52 Energy Efficiency Standards (EES) and 28 mandatory energy labels for a wide range of domestic, commercial, and selected industrial equipment. However, despite of the large number of standards issued, big challenges remain with how to ensure the standards keep up with the dynamic evolvement of technologies and appliance market after they enter effect. The current policy analysis methods adopted by the policy makers primarily focuses on standards making process and very limited attentions were paid on impact assessment and ex-post evaluation of standards and labeling systems, hence the effectiveness of active Energy Efficiency Standards has not been assessed timely and comprehensively. One major barrier of this is the lacking of assessment methods and market data. This thesis intends to tackle the above issues by developing a new policy analysis approach that can be used to assess the impact of energy efficiency standards and labeling with market data. This approach adopts a comprehensive analysis method that comprises three components: (1) Analysis of market data; (2) Quantification of energy savings potential; and (3) Benchmarking China’s EE standards to those of peer economies around the world. This integrated approach leads to three independent but complementary studies that provide evidence-based findings and policy recommendations for the improvement of China’s appliance standards.

The demand to integrate more features has significantly increased the complexity and power consumption of smart portable devices. Therefore extending the battery life-time has become a major challenge and new approaches are required to decrease the power consumed from the source. Traditionally the focus has been on reducing the dynamic power consumption of the digital circuits used in these devices. However as process technologies scale, reducing the dynamic power has become less effective due to the increased impact of the leakage power. Alternatively, a more effective approach to minimize the power consumption is to continuously optimize the ratio of the dynamic and leakage power while delivering the required performance. This works presents a novel power-aware system for dynamic minimum power point tracking of digital loads in portable applications. The system integrates a dc-dc converter power-stage and the supplied digital circuit. The integrated dc-dc converter IC utilizes a mixed-signal current program mode (CPM) controller to regulate the supply voltage of the digital load IC. This embedded converter inherently measures the power consumption of the load in real-time, eliminating the need for additional power sensing circuitry. Based on the information available in the CPM controller, a minimum power point tracking (MiPPT) controller sets the supply and threshold voltages for the digital load to minimize its power consumption while maintaining a target frequency. The 10MHz mixed-signal CPM controlled dc-dc converter and the digital load are fabricated in 0.13µm IBM technology. Experimental results verify that the introduced system results in up to 30% lower power consumption from the battery source.

The demand to integrate more features has significantly increased the complexity and power consumption of smart portable devices. Therefore extending the battery life-time has become a major challenge and new approaches are required to decrease the power consumed from the source. Traditionally the focus has been on reducing the dynamic power consumption of the digital circuits used in these devices. However as process technologies scale, reducing the dynamic power has become less effective due to the increased impact of the leakage power. Alternatively, a more effective approach to minimize the power consumption is to continuously optimize the ratio of the dynamic and leakage power while delivering the required performance. This works presents a novel power-aware system for dynamic minimum power point tracking of digital loads in portable applications. The system integrates a dc-dc converter power-stage and the supplied digital circuit. The integrated dc-dc converter IC utilizes a mixed-signal current program mode (CPM) controller to regulate the supply voltage of the digital load IC. This embedded converter inherently measures the power consumption of the load in real-time, eliminating the need for additional power sensing circuitry. Based on the information available in the CPM controller, a minimum power point tracking (MiPPT) controller sets the supply and threshold voltages for the digital load to minimize its power consumption while maintaining a target frequency. The 10MHz mixed-signal CPM controlled dc-dc converter and the digital load are fabricated in 0.13µm IBM technology. Experimental results verify that the introduced system results in up to 30% lower power consumption from the battery source.

abstract: Static CMOS logic has remained the dominant design style of digital systems for more than four decades due to its robustness and near zero standby current. Static CMOS logic circuits consist of a network of combinational logic cells and clocked sequential elements, such as latches and flip-flops that are used for sequencing computations over time. The majority of the digital design techniques to reduce power, area, and leakage over the past four decades have focused almost entirely on optimizing the combinational logic. This work explores alternate architectures for the flip-flops for improving the overall circuit performance, power and area. It consists of three main sections. First, is the design of a multi-input configurable flip-flop structure with embedded logic. A conventional D-type flip-flop may be viewed as realizing an identity function, in which the output is simply the value of the input sampled at the clock edge. In contrast, the proposed multi-input flip-flop, named PNAND, can be configured to realize one of a family of Boolean functions called threshold functions. In essence, the PNAND is a circuit implementation of the well-known binary perceptron. Unlike other reconfigurable circuits, a PNAND can be configured by simply changing the assignment of signals to its inputs. Using a standard cell library of such gates, a technology mapping algorithm can be applied to transform a given netlist into one with an optimal mixture of conventional logic gates and threshold gates. This approach was used to fabricate a 32-bit Wallace Tree multiplier and a 32-bit booth multiplier in 65nm LP technology. Simulation and chip measurements show more than 30% improvement in dynamic power and more than 20% reduction in core area. The functional yield of the PNAND reduces with geometry and voltage scaling. The second part of this research investigates the use of two mechanisms to improve the robustness of the PNAND circuit architecture. One is the use of forward and reverse body biases to change the device threshold and the other is the use of RRAM devices for low voltage operation. The third part of this research focused on the design of flip-flops with non-volatile storage. Spin-transfer torque magnetic tunnel junctions (STT-MTJ) are integrated with both conventional D-flipflop and the PNAND circuits to implement non-volatile logic (NVL). These non-volatile storage enhanced flip-flops are able to save the state of system locally when a power interruption occurs. However, manufacturing variations in the STT-MTJs and in the CMOS transistors significantly reduce the yield, leading to an overly pessimistic design and consequently, higher energy consumption. A detailed analysis of the design trade-offs in the driver circuitry for performing backup and restore, and a novel method to design the energy optimal driver for a given yield is presented. Efficient designs of two nonvolatile flip-flop (NVFF) circuits are presented, in which the backup time is determined on a per-chip basis, resulting in minimizing the energy wastage and satisfying the yield constraint. To achieve a yield of 98%, the conventional approach would have to expend nearly 5X more energy than the minimum required, whereas the proposed tunable approach expends only 26% more energy than the minimum. A non-volatile threshold gate architecture NV-TLFF are designed with the same backup and restore circuitry in 65nm technology. The embedded logic in NV-TLFF compensates performance overhead of NVL. This leads to the possibility of zero-overhead non-volatile datapath circuits. An 8-bit multiply-and- accumulate (MAC) unit is designed to demonstrate the performance benefits of the proposed architecture. Based on the results of HSPICE simulations, the MAC circuit with the proposed NV-TLFF cells is shown to consume at least 20% less power and area as compared to the circuit designed with conventional DFFs, without sacrificing any performance. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

With various new alternatives of low-cost sensor devices, there is a strong demand for large scale wireless sensor networks (WSN). Energy efficiency in routing is crucial for achieving the desired levels of longevity in these networks. Existing routing algorithms that do not combine information on transmission energies on links, residual energies at nodes, and the identity of data itself, cannot reach network capacity. A proof-of-concept routing algorithm that combines data aggregation with the minimum-weight path routing is studied in this thesis work. This new algorithm can achieve much larger network lifetime when there is redundancy in messages to be carried by the network, a practical reality in sensor network applications.