To solve these issues, in this thesis the consistent effort in developing a quick tools assisted IC design platform is presented. First, a reconfigurable solution is proposed for some analog/mixed-signal (AMS) system which requires flexibility to a certain extent, such as a reconfigurable RFID solution for different communicating distances. Second, for further demand of increasing the flexibility, a novel approach for ADA is presented, which provides a highly automatic design flow for analog circuits to realize the "SPEC (Specification) in, GDS out" goal. Considering all kinds of higher order effects and uncertainties under deep submicron or even more advanced technologies, reliable design and fastness in processing are the two major concerns instead of the traditional pure optimization for best performance. To get a good balance among performance, reliability and turnaround time, an Application-Specific design flow with in-built knowledge-based algorithms is applied to deal with ADA issues under advanced technologies, which can quickly provide a reliable design with performance good enough to meet the SPECs for common use. / Unlike the highly automatic flow for digital circuits design, analog design automation (ADA) is still far from mature. For mixed-signal applications, analog circuit occupies only a small part on the layout, but the design requires a considerable amount of time and effort, making ADA extremely attractive. However, there are a lot more considerations to cover in analog design flow than its digital counterparts. In addition, the ever downscaling IC means analog circuits have to face more and more small-size effects, insufficient modelings, and the inaccuracy of classic formulas, which are quite difficult to handle. To solve the problem, various tools and methods have been proposed, but all in a digital-like flow, which are trying to develop general algorithms to realize circuit and layout synthesis. Up to now there is still a lot of problems. / Hong, Yang. / Adviser: C.S. Choy. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 140-150). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

The advent of high-frequency silicon-based technologies has enabled the design of mixed-signal circuits that incorporate analog, RF, and digital circuit components to build cost-effective system-on-a-chip solutions. Emerging applications provide great incentive for continued scaling of transistor performance, requiring careful attention to mismatch, noise, and reliability concerns. If these mixed-signal technologies are to be employed within space-based electronic systems, they must also demonstrate reliability in radiation-rich environments. SiGe BiCMOS technology in particular is positioned as an excellent candidate to satisfy all of these requirements. The objective of this research is to develop predictive modeling tools that can be used to design new mixed-signal technologies and assess their reliability on Earth and in extreme environments. Ultimately, the goal is to illuminate the interaction of device- and circuit-level reliability mechanisms and establish best practices for modeling these effects in modern circuits. To support this objective, several specific areas have been targeted first, including a TCAD-based approach to identify performance-limiting regions in SiGe HBTs, measurement and modeling of carrier transport parameters that are essential for predictive TCAD, and measurement of device-level single-event transients to better understand the physical origins and implications for device design. These tasks provide the foundation for the bulk of this research, which addresses circuit-level reliability challenges through the application of novel mixed-mode TCAD techniques. All of the individual tasks are tied together by a guiding theme: to develop a holistic understanding of the challenges faced by emerging broadband technologies by coordinating results from material, device, and circuit studies.

In conventional design of power delivery networks (PDNs), the PDN impedance is required to be less than the target impedance over the frequency range of interest to minimize the IR drop and to suppress the inductive noise during data transitions. As a result, most PDNs in high-speed systems consist of power and ground planes to provide a low-impedance path between the voltage regulator module (VRM) and the integrated circuit (IC) on the printed circuit board (PCB). For off-chip signaling, charging and discharging signal transmission lines induce return currents on the power and ground planes. The return current always follows the path of least impedance on the reference plane closest to the signal transmission line. The return current path plays a critical role in maintaining the signal integrity of the bits propagating on the signal transmission lines. The problem is that the disruption between the power and ground planes induces return path discontinuities (RPDs), which create displacement current sources between the power and ground planes. The current sources excite the plane cavity and cause voltage fluctuations. These fluctuations are proportional to the plane impedance since the current is drawn through the PDN by the driver. Therefore, low PDN impedance is required for power supply noise reduction. Alternatively, methods of preventing RPDs can be used to suppress power supply noise. Using a power transmission line (PTL) eliminates the discontinuity between the power and ground planes, thereby preventing the RPD effects. In this approach, transmission lines replace the power plane for conveying power from the VRM to each IC on the PCB. The PTL-based PDN enables both power and signal transmission lines to be referenced to the same ground plane so that a continuous current path can be formed, unlike the power-plane-based PDN. As a result, a closed current loop is achieved, and the voltage fluctuation caused by RPDs is removed in idealistic situations. Without the RPD-related voltage fluctuation, reducing the PDN impedance is not as critical as in the power-plane-based approach. Instead, the impedance of the PTL is determined by the impedance of the signaling circuits. To use the PTL-based PDN in a practical signaling environment, several issues need to be solved. First, the dc drop coming from the source termination of the PTL needs to be addressed. The driver being turned on and off dictates the current flow through the PTL, causing the dc drop to be dynamic, which depends on the data pattern. Second, impedance mismatch between the PTL and termination can occur due to manufacturing variations. Third, an increase in the number of PCB traces should be addressed by devising a method to feed more than one driver with one PTL. Lastly, the power required to transmit 1 bit of data should be optimized for the PTL by using a new signaling scheme and adjusting the impedance of the signaling circuit. Constant flow of current through the PDN is one solution proposed to address the first two issues. Constant current removes the dynamic characteristics of the dc drop by inducing a fixed amount of dc drop over the PTL. Moreover, constant current keeps the PTL fully charged at all times, and thereby eliminates the process of repeatedly charging and discharging the power transmission line. The constant current PTL (CCPTL) scheme maintains constant current flow regardless of the input data pattern. Early results on the CCPTL scheme have been discussed along with the measurements. The CCPTL scheme severs the link between the current flowing through the PTL and the output data of the I/O driver connected to it. Also, it eliminates the charging and discharging process of the PTL, thereby completely eliminating power supply noise in idealistic situations. To reduce any associated power penalty, a pseudo-balanced PTL (PBPTL) scheme is also proposed using the PTL concept. A pseudo-balanced (PB) signaling scheme, which uses an encoding technique to map N-bit data onto M-bit encoded data with fixed number of 1s and 0s, is applied. When the PB signaling scheme is combined with the PTL, the jitter performance improves significantly as compared to currently practiced design approach.

Dissertation (Ph.D.)--Auburn University,2006. / Abstract. Vita. Includes bibliographic references (p.110-113).

Thesis (Ph. D.)--University of Texas at Austin, 2001. / Vita. Includes bibliographical references. Available also from UMI Company.

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The increasingly more sophisticated systems that are nowadays implemented on a single chip are placing stringent requirements on the test industry. New test strategies, equipment, and methodologies need to be developed to sustain the constant increase in demand for consumer and communication electronics. Techniques for built-in-self-test (BIST) and design-for-test (DFT) strategies have been proven to offer more feasible and economical testing solutions. / Previous works have been conducted to perform on-chip testing, characterization, and measurement of signals and components. The current thesis advances those techniques on many levels. In terms of performance, an increase of more than an order of magnitude in speed is achieved. 70-GHz (effective sampling) on-chip oscilloscope is reported, compared to 4-GHz and 10-GHz ones in previous state-of-the-art implementations. Power dissipation is another area where the proposed work offer a superior solution compared to previous alternatives. All the proposed circuits do not exceed a few milliWatts of power dissipation, while performing multi-GHz high-speed signal capture at a medium resolution. Finally, and possibly most importantly, all the proposed circuits for test rely on a different form of signal processing; the time-based approach. It is believed that this approach paves the path to a lot of new techniques and circuit design skills that can be investigated more deeply. As an integral part of the time-based processing approach for GHz signal capture, this thesis verifies the advantages of using time amplification. The use of such amplification in the time domain is materialized with experimental results from three specific integrated circuits achieving different tasks in GHz high-speed in-situ signal measurement and characterization. Advantages of using such time-based approach techniques, when combined with the use of a front-end time amplifier, include noise immunity, the use of synthesizable digital cells, and circuit building blocks that track the technology scaling in terms of area and speed.

FFT-based tests (e.g. gain, distortion, SNR, etc.) from a device-under-test (DUT) exhibit normal distributions when the measurement is repeated many times. Hence, a statistical approach to evaluate the accuracy of these measurements is traditionally applied. The noise in a DSP-based mixed-signal test system severely limits its measurement accuracy. Moreover, in high-speed sampled-channel applications the jitter-induced noise from the DUT and test equipment can severely impede accurate measurements. / A new digitizer architecture and post-processing methodology is proposed to increase the measurement accuracy of the DUT and the test equipment. An optimal digitizer design is presented which removes any measurement bias due to noise and greatly improves measurement repeatability. Most importantly, the presented system improves accuracy in the same test time as any conventional test. / An integrated mixed-signal test core was implemented in TSMC's 0.18 mum mixed-signal process. Experimental results obtained from the mixed-signal integrated test core validate the proposed digitizer architecture and post processing technique. Bias errors were successfully removed and measurement variance was improved by a factor of 5.

Thesis (Ph. D.)--Oregon State University, 2008. / Printout. Includes bibliographical references (leaves 79-82). Also available on the World Wide Web.