The exploitation of the theoretically enormous capacity achieved by the multiple transmit and receive antennas systems (MIMO) in a rich scattering communication channel has been the subject of vast body of research on the field of MIMO. In particular, the Vertically-layered Bell Laboratories Layered Space-Time (V-BLAST) is a well known MIMO architecture which has demonstrated the enormous capacity of 20-40 bit/s/Hz in an indoor propagation environment with realistic SNR and error rates. However, due to the intensive computation involved, it would be difficult to implement this architecture for high data rate communication systems. Some works have been done to improve the receiver complexity and performance by coding techniques, by different detection architectures. In this thesis, we have focused on QR-based decoders for V-BLAST MIMO. For a suitable V-BLAST detection implementation, we need to carefully consider the problem from algorithmic, arithmetic and architectural aspects. At the algorithmic level, the numerical stability and robustness should be considered. At the arithmetic level, signal quantization is important, and, at the architectural level, parallelism and pipelining require attention. We have performed the above mentioned optimization on the 1-pass QR factorization with back substitution SIC (Symbol Interference Cancellation) decoder in chapter 3. At first optimizations are made on the proposed algorithm and architecture using MATLAB simulations. Then a new architecture for the QR-factorizer as the core processor of the V-BLAST decoder is developed in chapter 4. This architecture uses only two low complexity CORDIC (Coordinate rotation digital computer) processors. The parameterized feature of the controller and address generator blocks of this architecture has provided a scalable architecture for the implementation of QR factorization for square matrix of any dimension. The reduced hardware complexity of the processors and its simple parameterized controller are two outstanding features of the architecture, resulting in a more suitable alternative architecture for QR factorization than traditional triangular systolic arrays. In the next phase of the research, new hardware architectures of the back substitution SIC decoder was developed for a 4 X 4 MIMO system with 16-QAM constellation scheme in chapter 5. The division operation for back substitution needs a complex hardware, and results in the numerical instability. In the proposed hardware the elimination of division and modification of multiplier has reduced the hardware complexity and led to numerical stability. In addition the pre decoding block was designed and optimized in terms of number of the pipeline registers and CORDIC rotator processors. The developed hardware is capable of processing 20 vectors data burst and results in a throughput of 149 Mb/s. The FPGA (Field Programmable Gate Array) and ASIC (Application specific Integrated Circuit) implementations of the proposed optimized architecture are presented in Chapter 5. We found that the equivalent gates and the core area in our design is less than 30% of other designs and the maximum clock frequency and the throughput is higher (175 %) than other works. Finally the improvements of the BER performance using the branching method and parallel architectures are presented in chapter 6. In this supplementary part to back substitution OSIC decoder, the final symbol vector is selected from 2 or 8 potential candidates based on the minimum Euclidean norm, which improves the BER between 3 to 7 db and gives a very close match to the original V-BLAST performance.

The exploitation of the theoretically enormous capacity achieved by the multiple transmit and receive antennas systems (MIMO) in a rich scattering communication channel has been the subject of vast body of research on the field of MIMO. In particular, the Vertically-layered Bell Laboratories Layered Space-Time (V-BLAST) is a well known MIMO architecture which has demonstrated the enormous capacity of 20-40 bit/s/Hz in an indoor propagation environment with realistic SNR and error rates. However, due to the intensive computation involved, it would be difficult to implement this architecture for high data rate communication systems. Some works have been done to improve the receiver complexity and performance by coding techniques, by different detection architectures. In this thesis, we have focused on QR-based decoders for V-BLAST MIMO. For a suitable V-BLAST detection implementation, we need to carefully consider the problem from algorithmic, arithmetic and architectural aspects. At the algorithmic level, the numerical stability and robustness should be considered. At the arithmetic level, signal quantization is important, and, at the architectural level, parallelism and pipelining require attention. We have performed the above mentioned optimization on the 1-pass QR factorization with back substitution SIC (Symbol Interference Cancellation) decoder in chapter 3. At first optimizations are made on the proposed algorithm and architecture using MATLAB simulations. Then a new architecture for the QR-factorizer as the core processor of the V-BLAST decoder is developed in chapter 4. This architecture uses only two low complexity CORDIC (Coordinate rotation digital computer) processors. The parameterized feature of the controller and address generator blocks of this architecture has provided a scalable architecture for the implementation of QR factorization for square matrix of any dimension. The reduced hardware complexity of the processors and its simple parameterized controller are two outstanding features of the architecture, resulting in a more suitable alternative architecture for QR factorization than traditional triangular systolic arrays. In the next phase of the research, new hardware architectures of the back substitution SIC decoder was developed for a 4 X 4 MIMO system with 16-QAM constellation scheme in chapter 5. The division operation for back substitution needs a complex hardware, and results in the numerical instability. In the proposed hardware the elimination of division and modification of multiplier has reduced the hardware complexity and led to numerical stability. In addition the pre decoding block was designed and optimized in terms of number of the pipeline registers and CORDIC rotator processors. The developed hardware is capable of processing 20 vectors data burst and results in a throughput of 149 Mb/s. The FPGA (Field Programmable Gate Array) and ASIC (Application specific Integrated Circuit) implementations of the proposed optimized architecture are presented in Chapter 5. We found that the equivalent gates and the core area in our design is less than 30% of other designs and the maximum clock frequency and the throughput is higher (175 %) than other works. Finally the improvements of the BER performance using the branching method and parallel architectures are presented in chapter 6. In this supplementary part to back substitution OSIC decoder, the final symbol vector is selected from 2 or 8 potential candidates based on the minimum Euclidean norm, which improves the BER between 3 to 7 db and gives a very close match to the original V-BLAST performance.

As the characteristics of mobile radio channels vary over time, transmit power must be controlled accordingly to ensure that the received signal level is within the receiver's sensitivity. As a consequence, modern mobile radio systems employ power control to regulate the received signal level such that it is neither less nor excessively larger than receiver sensitivity in order to maintain adequate service quality. In this context, speech quality measurement is an important aspect in the delivery of speech services as it will impact satisfaction of customers as well as the usage of precious system resources. A variety of techniques for speech quality measurement has been produced over the last few years as result of tireless research in the area of perceptual speech quality estimation. These are mainly based on psychoacoustic models of the human auditory systems. However, these techniques cannot be directly applied for real-time communication purposes as they typically require a copy of the transmitted and received speech signals for their operation. This thesis presents a novel technique of incorporating perceptual speech quality metrics with power control for mobile radio systems. The technique allows for standardized perceptual speech quality measurement algorithms to be used for in-service measurement of speech quality. The accuracy of the proposed Real-Time Perceptual Speech Quality Measurement (RTPSQM) technique with respect to measuring speech quality is first validated by extensive simulations. On this basis, RTPSQM is applied to power control in the Global System for Mobile (GSM) communication and the Universal Mobile Telecommunication System (UMTS). It is shown by simulations that the use of perceptual-based power control in GSM and UMTS outperforms conventional power control in terms of reducing the transmitter signal power required for providing adequate speech quality. This in turn facilitates the observed increase in system capacity and thus offers better utilization of available system resources. To enable an analytical performance assessment of perceptual speech quality metrics in power control, the mathematical frameworks for conventional and perceptual-based power control are derived. The derivations are performed for Code Division Multiple Access (CDMA) systems and kept as generic as possible. Numerical results are presented which could be used in a system design to readily find the Erlang capacity per cell for either of the considered power control algorithms.

Zugl.: Saarbrücken, Univ., Diss., 2006

Thesis (Ph. D.)--University of Western Australia, 2007.

Thesis (M.Eng.(Electronic Engineering))--University of Pretoria, 2008. / Summaries in Afrikaans and English. Includes bibliographical references (leaves [92]-99).

Thesis (M.App.Sc.) - Carleton University, 2002. / Includes bibliographical references (p. 124-127). Also available in electronic format on the Internet.

Thesis (Ph.D.) - Carleton University, 2006. / Includes bibliographical references (p. 156-164). Also available in electronic format on the Internet.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 138-145). Also available via the Internet.

Thesis (Ph. D.)--Ohio State University, 2005. / Title from first page of PDF file. Includes bibliographical references (p. 164-173).