Electronic design automation (EDA) tools play a central role in bridging the productivity gap for designing complex hardware systems. However, with an increase in the size and complexity of today's design requirements, current methodologies and EDA tools are unable to effectively mitigate the further widening of productivity gap. It is estimated that testing and verification takes 2/3rd of the total development time of complex hardware systems. Functional simulation forms the main stay of testing and verification process and is the most widely used technique for testing and verification. Most of the simulation algorithms and their implementations are designed for uniprocessor systems that cannot easily leverage the parallelism in multi-core and GPU platforms. For example, logic simulation often uses levelized sequential algorithms, whereas the discrete-event simulation frameworks for Verilog, VHDL and SystemC employ concurrency in the form of multi-threading to given an illusion of the inherent parallelism present in circuits. However, the discrete-event model of computation requires a global notion of an event-queue, which makes improving its simulation performance via parallelization even more challenging. This work investigates automatic parallelization of simulation algorithms used to simulate hardware models. In particular, we focus on parallelizing the simulation of hardware designs described at the RTL using SystemC/HDL with examples to clearly describe the parallelization. Even though multi-cores and GPUs other parallelism, efficiently exploiting this parallelism with their programming models is not straightforward. To overcome this, we also focus our research on building intelligent translators to map simulation applications onto multi-cores and GPUs such that the complexity of the low-level programming models is hidden from the designers. / Master of Science

As technology advances, embedded systems become increasingly complex, with embedded software implemented on platforms with many processors running in parallel. Testing such software on hardware might not always be possible and, when possible, can be time-consuming and costly. An alternative to using real hardware is to use simulation methods instead. This thesis project explores one approach using multiple parallel Linux processes and barrier synchronization for simulating embedded software. An implementation consisting of a simulation engine and multiple simulated cores was designed. This implementation is evaluated for accuracy and speed by comparing it to another barrier synchronization tool that does not use parallelism. The results indicate that the sequential tool has an accuracy error that is doubled for every added simulated core. However, the parallel simulator can handle these situations without any accuracy error increase. Regarding speed, the parallel implementation is approximately 30% slower for longer simulations. However, simulation speed could be increased by utilizing some unused potential in the parallelism. / I takt med den tekniska utvecklingen blir de inbyggda systemen alltmer komplexa, med inbyggd programvara implmenterad på plattformar med många processorer som körs parallellt. Att testa sådan programvara på hårdvara är inte alltid möjligt och, när det är möjligt, kan det vara tidsödande och kostsamt. Ett alternativ till att använda riktig hårdvara är att istället använda simuleringsmetoder. I detta examensarbete undersöks en metod som använder flera parallella Linux-processer och barriärsynkronisering för simulering av inbyggd mjukvara. En implementering bestående av en simuleringsmotor och flera simulerade kärnor framställs. Denna implementering utvärderas för noggrannhet och hastighet genom att jämföra den med ett annat verktyg med barriärsynkronisering som inte använder parallellism. Resultaten indikerar att det sekventiella verktyget har ett noggrannhetsfel som fördubblas för varje tillagd simulerad kärna. Den parallella simulatorn kan dock hantera dessa situationer utan att noggrannhetsfelet ökar. När det gäller hastighet är den parallella implementeringen ungefär 30% långsammare för längre simulationer. Simuleringshastigheten kan möjligtvis ökas genom att utnyttja en del oanvänd potential i parallellismen.

De nos jours, la validation des unités de contrôle électronique ECU se fonde généralement sur la simulationHardware-In-the-Loop où les systèmes physiques qui manquent sont modélisés à l’aide deséquations différentielles hybrides. La complexité croissante de ce type de modèles rend le compromisentre le temps de calcul et la précision de la simulation difficile à satisfaire. Cette thèse étudie et proposedes méthodes d’analyse et d’expérimentation destinées à la co-simulation temps-réel ferme de modèlesdynamiques hybrides. Elle vise notamment à définir des solutions afin d’exploiter plus efficacement leparallélisme fourni par les architectures multi-coeurs en utilisant de nouvelles méthodes et paradigmesde l’allocation des ressources. La première phase de la thèse a étudié la possibilité d’utiliser des méthodesd’intégration numérique permettant d’adapter l’ordre comme la taille du pas de temps ainsi quede détecter les événements et ceci dans le contexte de la co-simulation modulaire avec des contraintestemps-réel faiblement dures. De plus, l’ordre d’exécution des différents modèles a été étudié afin dedémontrer l’influence du respect des dépendances de données entre les modèles couplés sur les résultatsde la simulation. Nous avons proposé pour cet objectif, une nouvelle méthode de co-simulationqui permet le parallélisme complet entre les modèles impliquant une accélération supra-linéaire sanspour autant ajouter des erreurs liées à l’ordre d’exécution. Enfin, les erreurs de retard causées par lataille de pas de communication entre les modèles ont été améliorées grâce à une nouvelle méthoded’extrapolation par contexte des signaux d’entrée. Toutes les approches proposées visent de manièreconstructive à améliorer la vitesse de simulation afin de respecter les contraintes temps-réel, tout engardant la qualité et la précision des résultats de simulation sous contrôle. Ces méthodes ont été validéespar plusieurs essais et expériences sur un modèle de moteur à combustion interne et intégrées àun prototype du logiciel xMOD. / Nowadays the validation of Electronic Control Units ECUs generally relies on Hardware-in-The-Loopsimulation where the lacking physical systems are modeled using hybrid differential equations. Theincreasing complexity of this kind of models makes the trade-off between time efficiency and the simulationaccuracy hard to satisfy. This thesis investigates and proposes some analytical and experimentalmethods towards weakly-hard real-time co-simulation of hybrid dynamical models. It seeks in particularto define solutions in order to exploit more efficiently the parallelism provided by multi-core architecturesusing new methods and paradigms of resource allocation. The first phase of the thesis studied the possibilityof using step-size and order control numerical integration methods with events detection in thecontext of real-time modular co-simulation when the time constraints are considered weakly-hard. Moreover,the execution order of the different models was studied to show the influence of keeping or not thedata dependencies between coupled models on the simulation results. We proposed for this aim a newmethod of co-simulation that allows the full parallelism between models implying supra-linear speed-upswithout adding errors related to their execution order. Finally, the delay errors due to the communicationstep-size between the models were improved thanks to a proposed context-based inputs extrapolation.All proposed approaches target constructively to enhance the simulation speed for the compliance toreal-time constraints while keeping the quality and accuracy of simulation results under control and theyare validated through several test and experiments on an internal combustion engine model and integratedto a prototype version of the xMOD software.