Orientador: Rodolfo Jardim de Azevedo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-15T06:45:02Z (GMT). No. of bitstreams: 1 Hoyos_FranciscoRafaelLorenzo_M.pdf: 663609 bytes, checksum: 9bf12382c86fbf499da0f33713f074a4 (MD5) Previous issue date: 2009 / Resumo: O Cell Broadand Engine (Cell BE) é um processador com arquitetura de múltiplos núcleos heterogêneos, voltado para o uso em aplicações de alto desempenho. Talvez mais conhecido como o processador do Playstation 3 da Sony, ele também está presente aos milhares no supercomputador Roadrunner da IBM. Entretanto, o SDK do Cell BE não suporta o desenvolvimento de aplicações sem Java. Como é sabido, Java é uma das linguagens mais utilizadas hoje em dia, nas mais variadas plataformas de hardware e para quase todos os tipos de aplicações. Este trabalho introduz um novo modelo para a execução de programas Java no Cell BE. Esse modelo permite ao programador Java executar tarefas (partes do código Java do programa principal) nos Synergistic Processing Elements (SPE), que são núcleos especializados do Cell BE, maiores responsáveis pelo grande poder de processamento desse chip. Enquanto outras soluções tentam esconder completamente a arquitetura de múltiplos núcleos heterogêneos do Cell BE, a nova proposta expõe um modelo de memória explicitamente distribuída, habilitando o programador Java a definir exatamente qual código deve executar nos SPEs. A viabilidade do modelo é então demonstrada através da melhoria de desempenho obtida consistentemente com vários programas executados em uma máquina virtual Java modificada para suportar a plataforma Cell BE. Com seis SPEs, esses programas executam, em média, aproximadamente duas vezes mais rápido do que os mesmos programas na máquina virtual Java original / Abstract: The Cell Broadband Engine (Cell BE) is a processor with a heterogeneous multicore architecture, targeted at high performance applications. Perhaps best known as the processor of Sony's PlayStation 3, it is also used (thousands of them) in the IBM Roadrunner supercomputer. However, the Cell BE SDK does not support Java application development. It is well known that Java is currently one of the most widely used languages, being present on many different hardware platforms and in almost all types of applications. This work introduces a new model for the execution of Java programs on the Cell BE. Such model allows the Java programmer to execute tasks (pieces of the main program's Java code) on the Synergistic Processing Elements (SPE), which are highly specialized cores in the Cell BE and are the main source of the chip's huge processing power. While other solutions try to completely hide the Cell BE's heterogeneous multicore architecture, this new proposal exposes an explicit distributed memory model, empowering the Java programmer to define exactly what code runs on the SPEs. The feasibility of the model is demonstrated by means of consistent performance improvements achieved with several programs executed on a Java virtual machine, which has been modified to support the Cell BE platform. With six SPEs those programs run, on average, around twice as fast as the same programs on the original Java virtual machine / Mestrado / Linguagens de Programação / Mestre em Ciência da Computação

Avec l’augmentation du nombre de cœurs, les problèmes de congestion sont commencé avec les interconnexions conventionnelles. Afin de remédier à ces défis, WiNoCoD projet (Wired RF Network-on-Chip Reconfigurable-on-Demand) a été initié par le financement de l’Agence Nationale de Recherche (ANR). Ce travail de thèse contribue à WiNoCoD projet. Une structure de contrôleur de RF est proposé pour l’interconnexion OFDMA de WiNoCoD et plusieurs algorithmes d’allocation de bande passante efficaces (distribués et centralisés) sont développés, concernant les demandes et contraintes très spécifiques de l’environnement sur-puce. Un protocole innovante pour l’arbitrage des sous-porteuses pour des longueurs bimodales de paquets sur-puce, qui ne nécessite aucun signalisation supplémentaire est introduit. Utilisation des ordres de modulation élevés avec plus grande consommation d’énergie est évaluée. / With rapidly increasing number of cores on a single chip, scalability problems have arised due to congestion and latency with conventional interconnects. In order to address these issues, WiNoCoD project (Wired RF Network-on-Chip Reconfigurable-on-Demand) has been initiated by the support of French National Research Agency (ANR). This thesis work contributes to WiNoCoD project. A special RF controller structure has been proposed for the OFDMA based wired RF interconnect of WiNoCoD. Based on this architecture, effective bandwidth allocation algorithms have been presented, concerning very specific requirements and constraints of on-chip environment. An innovative subcarrier allocation protocol for bimodal packet lengths of cache coherency traffic has been presented, which is proven to decrease average latency significantly. In addition to these, effective modulation order selection policies for this interconnect have been introduced, which seeks the optimal delay-power trade-off.

L’utilisation de plusieurs cœurs pour l’exécution des applications mobiles sera l’approche dominante dans les systèmes embarqués pour les prochaines années. Cette approche permet en générale d’augmenter les performances du système sans augmenter la vitesse de l’horloge. Grâce à cela, la consommation d’énergie reste modérée. Toutefois, la concurrence entre les tâches doit être exploitée afin d’améliorer les performances du système dans les différentes situations où l’application peut s’exécuter. Les applications multimédias comme la vidéoconférence ou la vidéo haute définition, ont de nombreuses nouvelles fonctionnalités qui nécessitent des calculs complexes par rapport aux normes précédentes de codage vidéo. Ces applications créent une charge de travail très importante sur les systèmes multiprocesseurs. L’exploitation du parallélisme pour les applications multimédia, comme le codec vidéo H.264/AVC, peut se faire à différents niveaux : au niveau de données ou bien au niveau tâches. Dans le cadre de cette thèse de doctorat, nous proposons de nouvelles solutions pour une meilleure exploitation du parallélisme dans les applications multimédia sur des systèmes embarqués ayant une architecture parallèle symétrique (ou SMP pour Symmetric Multi-Processor). Des approches innovantes pour le décodeur H.264/AVC qui traitent des composantes de couleur et des blocs de l’image en parallèle sont proposées et expérimentées. / Parallel computing is currently the dominating architecture in embedded systems. Concurrency improves the performance of the system rather without increasing the clock speed which affects the power consumption of the system. However, concurrency needs to be exploited in order to improve the system performance in different applications environments. Multimedia applications (real-Time conversational services such as video conferencing, video phone, etc.) have many new features that require complex computations compared to previous video coding standards. These applications have a challenging workload for future multiprocessors. Exploiting parallelism in multimedia applications can be done at data and functional levels or using different instruction sets and architectures. In this research, we design new parallel algorithms and mapping methodologies in order to exploit the natural existence of parallelism in multimedia applications, specifically the H.264/AVC video decoder. We mainly target symmetric shared-Memory multiprocessors (SMPs) for embedded devices such as ARM Cortex-A9 multicore chips. We evaluate our novel parallel algorithms of the H.264/AVC video decoder on different levels: memory load, energy consumption, and execution time.