Not available / text

This thesis presents design automation methodologies for extensible processor platforms in application specific domains. The work presents first a single processor approach for customization; a methodology that can rapidly create different processor configurations by the removal of unused instructions sets from the architecture. A profile directed approach is used to identify frequently used instructions and to eliminate unused opcodes from the available instruction pool. A coprocessor approach is next explored to create an SoC (System-on-Chip) to speedup the application while reducing energy consumption. Loops in applications are identified and accelerated by tightly coupling a coprocessor to an ASIP (Application Specific Instruction-set Processor). Latency hiding is used to exploit the parallelism provided by this architecture. A case study has been performed on a JPEG encoding algorithm; comparing two different coprocessor approaches: a high-level synthesis approach and our custom coprocessor approach. The thesis concludes by introducing a heterogenous multi-processor system using ASIPs as processing entities in a pipeline configuration. The problem of mapping each algorithmic stage in the system to an ASIP configuration is formulated. We proposed an estimation technique to calculate runtimes of the configured multiprocessor system without running cycle-accurate simulations, which could take a significant amount of time. We present two heuristics to efficiently search the design space of a pipeline-based multi ASIP system and compare the results against an exhaustive approach. In our first approach, we show that, on average, processor size can be reduced by 30%, energy consumption by 24%, while performance is improved by 24%. In the coprocessor approach, compared with the use of a main processor alone, a loop performance improvement of 2.57x is achieved using the custom coprocessor approach, as against 1.58x for the high level synthesis method, and 1.33x for the customized instruction approach. Energy savings are 57%, 28% and 19%, respectively. Our multiprocessor design provides a performance improvement of at least 4.03x for JPEG and 3.31x for MP3, for a single processor design system. The minimum cost obtained using our heuristic was within 0.43% and 0.29% of the optimum values for the JPEG and MP3 benchmarks respectively.

This dissertation presents the design and development of a multi-processor logic simulator. After an introduction to parallel processing, the concept of distributed simulation is described as well as the possibility of deadlock in a distributed system. It is proven that the proposed system does not deadlock. Next, the modeling techniques are discussed along with the timing mechanisms used for logic simulation. A new approach, namely process oriented simulation is studied in depth. It is shown that modeling for this kind of simulation is more efficient regarding modeling ease, computer memory and simulation time, than existing simulation methods. The hardware design of the multi-processor system and the algorithms for synchronization and signal interchange between the processors are presented next. An algorithm for an efficient partitioning of the digital network to be simulated among the processors of the system is also described. Apart from the simulation of a single digital network, the simulator can also be used for fault simulation and design verification. Regarding fault simulation, the fault injection and fault detection techniques are presented. The experimental results obtained by running the multi-processor simulator are compared with the theoretical estimates as well as with results obtained by other multi-processor systems. The comparison shows that the proposed simulator exhibits the estimated performance. Finally, the design of a common bus interface is given. This interface will connect the processors of the system directly without the intervention of a hard disk which was used for the development and testing of the system. / Ph. D.