In multiprocessor systems, cache memories serve two purposes, namely the reduction of the average access time to the shared memory and the minimization of interconnection network requirements for each processor. However, in a cache, interference between operations from the processor and operations for data coherence from other caches degrades the cache performance. We propose a cache with only one single dual-port directory which can be operated for both processor accesses and coherence operations simultaneously. The cache can reach high performance at low cost. This cache also has a data-coherence-protocol-independent structure. To evaluate the cache performance in a multiprocessor environment, two simulation models are created. The system performance is extensively simulated. The results show that the single dual-port directory cache system has higher performance than that obtained by a system with single one-port directory caches. Other design parameters such as cache size, line size, and associativity on system performance are also discussed. Furthermore, simulations indicate that use of multiple buses significantly increases system performance. In order to improve the reliability of the proposed cache, we design a tag self-purge mechanism and a comparator checker at low cost in the cache management unit. We also propose a new design that provides combinational totally self-checking checkers for 1/n codes in CMOS technology, which can be used to build such a checker for the 1/3 code. Moreover, the total hardware overhead is less than 42%, as compared to the traditional single directory cache management unit. The dissertation includes a new optimal test algorithm with a linear test time complexity, which can be used to test the cache management unit by either the associated processor or external test equipment. An efficient built-in self-testing variant of the proposed algorithm is also discussed. The hardware overhead of such a scheme is much less than the traditional approach. / Graduate

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Thesis (Ph. D.)--University of Wisconsin--Madison, 1993. / Typescript. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references (leaves 306-317).

Thesis (Ph. D.)--University of Wisconsin--Madison, 1983. / Typescript. Vita. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references (leaves 205-212).

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Throughput and latency are critical parameters in multiprocessor interconnection networks. These parameters are governed by the combination of routing node and interconnect performance. Recent years have seen several new interconnect technologies reach the stage of maturity where they may be applied in practical systems. One such technology is free-space optical interconnect. The problems of wiring density, low data-rates and limited integrated circuit (IC) pin-out are neatly side-stepped by the use of optical interconnect. In order to make practical use of optical interconnects, packet routing node data rates must increase by an order of magnitude or more. At the same time, latency cannot be sacrificed as it is critical to the performance of multi-processor systems. One possible avenue to meeting the required performance is to re-examine the hardware cost of packet router architectures and attempt to improve them. The research presented in this thesis attempts to do exactly that. The result of this research is a packet router architecture known as the Cellular Router. The router allows massive throughput, while maintaining low latency. The architecture is designed to minimise silicon area and maximise achievable clock rate in any given fabrication process. The router is scalable, in the sense that area requirements increase linearly along one axis in proportion to increased throughput. This thesis describes a novel packet router architecture. It is a compact, power efficient, scalable design that is capable of exceptionally high throughput. The Cellular Router allows the benefits of free-space optical interconnects to be effectively utilised in multi-processor systems.

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Thesis (M.S.)--Ohio University, November, 1984. / Title from PDF t.p.