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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Dynamic resource allocation and interprocess communication in multiprocessor systems

Fanourgiakis, Demetrios. January 1978 (has links)
No description available.
2

Multiprocessor scheduling with memory constraints

Lau, H. T. (Hang Tong), 1952- January 1978 (has links)
No description available.
3

Dynamic resource allocation and interprocess communication in multiprocessor systems

Fanourgiakis, Demetrios. January 1978 (has links)
No description available.
4

Extending the scalable coherent interface for large-scale shared-memory multiprocessors

Johnson, Ross Evan. January 1900 (has links)
Thesis (Ph. D.)--University of Wisconsin--Madison, 1993. / Typescript. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references (leaves 306-317).
5

Concurrency control and recovery in multiprocessor database machines design and performance evaluation /

Agrawal, Rakesh. January 1900 (has links)
Thesis (Ph. D.)--University of Wisconsin--Madison, 1983. / Typescript. Vita. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references (leaves 205-212).
6

A high performance fault tolerant cache memory for multiprocessors

Luo, Xiao 09 July 2018 (has links)
In multiprocessor systems, cache memories serve two purposes, namely the reduction of the average access time to the shared memory and the minimization of interconnection network requirements for each processor. However, in a cache, interference between operations from the processor and operations for data coherence from other caches degrades the cache performance. We propose a cache with only one single dual-port directory which can be operated for both processor accesses and coherence operations simultaneously. The cache can reach high performance at low cost. This cache also has a data-coherence-protocol-independent structure. To evaluate the cache performance in a multiprocessor environment, two simulation models are created. The system performance is extensively simulated. The results show that the single dual-port directory cache system has higher performance than that obtained by a system with single one-port directory caches. Other design parameters such as cache size, line size, and associativity on system performance are also discussed. Furthermore, simulations indicate that use of multiple buses significantly increases system performance. In order to improve the reliability of the proposed cache, we design a tag self-purge mechanism and a comparator checker at low cost in the cache management unit. We also propose a new design that provides combinational totally self-checking checkers for 1/n codes in CMOS technology, which can be used to build such a checker for the 1/3 code. Moreover, the total hardware overhead is less than 42%, as compared to the traditional single directory cache management unit. The dissertation includes a new optimal test algorithm with a linear test time complexity, which can be used to test the cache management unit by either the associated processor or external test equipment. An efficient built-in self-testing variant of the proposed algorithm is also discussed. The hardware overhead of such a scheme is much less than the traditional approach. / Graduate
7

Multiprocessor scheduling with memory constraints

Lau, H. T. (Hang Tong), 1952- January 1978 (has links)
No description available.
8

A design synthesis environment for DSP algorithms represented by shift-invariant flow graphs

Kim, Hyeong-Kyo 05 1900 (has links)
No description available.
9

Hardware design of a multiprocessor system with five Motorola MC6809E microprocessors

Gamez, Carlos A. January 1984 (has links)
Thesis (M.S.)--Ohio University, November, 1984. / Title from PDF t.p.
10

Modélisation et optimisation de systèmes multiprocesseurs hiérarchiques dans un contexte d'intégration à très grande échelle /

Ho, Tuong Vinh, January 1994 (has links)
Mémoire (M.Eng.)-- Université du Québec à Chicoutimi, 1994. / Résumé disponible sur Internet. CaQCU Document électronique également accessible en format PDF. CaQCU

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