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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Solution-processed zinc-tin oxide thin-film transistors and circuit applications

Lee, Chen-Guan, 1982- 21 June 2011 (has links)
Amorphous oxide semiconductors are of potential interest in the display industry due to their high carrier mobility, transparency at visible wavelengths and excellent operational stability. In this dissertation, n-channel zinc-tin oxide thin-film transistors are fabricated based on a solution-based deposition approach, which allows low fabrication cost and high throughput. The effects of device configuration and process conditions on transistor performance are investigated, and circuit applications including inverters, amplifiers, and ring oscillators are demonstrated. Charge transport in the zinc-tin oxide field-effect transistors is also investigated. A transition from thermally-activated to band-like transport is observed with increasing carrier concentration in high mobility samples, which agrees well with the key predictions of the multiple trap and release model and also Mott’s mobility edge model. In addition, velocity distribution of charge carriers is studied with a time-resolved technique. This provides a more detailed picture of charge transport in field-effect transistors. P-channel organic semiconductor field-effect transistors are also investigated with a view to combine them with n-channel amorphous oxide transistors to create a hybrid organic-inorganic complementary technology. / text
2

A Low Temperature Study of the N-Channel MOS FET

Cizmar , Edward S. 05 1900 (has links)
Scope and contents: The static and dynamic electrical characteristics of silicon n-channel MOS FETs are studied down to cryogenic temperatures. Particular emphasis is directed towards the effect of interface states on the temperature dependence of both the pinch-off voltage and 1/f noise. / No abstract included. / Thesis / Master of Engineering (MEngr)
3

Sub-Threshold Slope Modeling & Gate Alignment Issues In Tunnel Field Effect Transistor

Ramesha, A 08 1900 (has links)
The Tunnel Field Effect Transistor (TFET) with sub-60mV/decade Sub-threshold slope and extremely high ION/IOFF ratio has attracted enough attention for low standby power (LSTP) applications where the battery life is very important. So far research in this area has been limited to numerical simulation and experimental analysis. It is however extremely necessary to develop compact models for TFET in order to use them in nano-scale integrated circuit design and simulation. In this work, for the first time, we develop analytical Sub-threshold slope model for n-channel double gate TFET (nDGTFET). Unlike conventional FETs, current in TFET is mainly controlled by the band-to-band tunneling mechanism at source/channel interface. As the total drain current is proportional to band-to-band generation rate, the main challenge in the present work is to find an explicit relationship between average electric field over the tunneling path and the applied gate voltage under nonlocal tunneling condition. Two dimensional Poisson’s equation (with Laplace approximation)is first solved in a rectangular coordinate system in order to obtain analytical expression for electron energy distribution over the channel region.Kane’s Model[J. Phy. Chem.Solids 12(181)1959]for band-to-band tunneling along with some analytical approximation techniques are then used to derive the expression for the Sub-threshold slope under nonlocal tunneling conditions. This Sub-threshold slope model is verified against professional numerical device simulator (MEDICI) for different device geometries. Being an asymmetric device, TFET fabrication suffers from source misalignment with gate. As the doping in source and drain-gate are different, conventional-FET-like self-aligned gate stack formation is not possible for TFET. Such misalignment, at source side, seriously degrades the performance of TFETs. To overcome this problem, in this work we explore the possibility of using “gate replacement” technique for TFET fabrication. We first develop process flow for single gate bulk nTFET, and then we extend it to n-channel double gate TFET (nDGTFET) using modified FinFET process. Good alignments between source and gate are observed with TCAD-simulations in both the cases.

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