<p>Xilinx Virtex II Pro FPGA with integrated PowerPC core offers an opportunity to implementing a software and hardware codesign. The software application executes on the PowerPC processor while the FPGA implementation of hardware cores coprocess with PowerPC to achieve the goals of acceleration. Another benefit of coprocessing with the hardware acceleration core is the release of processor load. This thesis demonstrates such an FPGA based software and hardware codesign by implementing a real time video processing project on Xilinx ML310 development platform which is featured with a Xilinx Virtex II Pro FPGA. The software part in this project performs video and memory interface task which includes image capture from camera, the store of image into on-board memory, and the display of image on a screen. The hardware coprocessing core does a contrast enhancement function on the input image. To ease the software development and make this project flexible for future extension, an Embedded Operating System MontaVista Linux is installed on the ML310 platform. Thus the software video interface application is developed using Linux programming method, for example the use of Video4Linux API. The last but not the least implementation topic is the software and hardware interface, which is the Linux device driver for the hardware core. This thesis report presents all the above topics of Operating System installation, video interface software development, contrast enhancement hardware implementation, and hardware core’s Linux device driver programming. After this, a measurement result is presented to show the performance of hardware acceleration and processor load reduction, by comparing to the results from a software implementation of the same contrast enhancement function. This is followed by a discussion chapter, including the performance analysis, current design’s limitations and proposals for improvements. This report is ended with an outlook from this master thesis.</p>

Over the past decade, solid-state nanopores have emerged as a versatile tool for the detection and characterization of single molecules, showing great promise in the field of personalized medicine as diagnostic and genotyping platforms. While solid-state nanopores offer increased durability and functionality over a wider range of experimental conditions compared to their biological counterparts, reliable fabrication of low-noise solid-state nanopores remains a challenge. In this thesis, a methodology for treating nanopores using high electric fields in an automated fashion by applying short (0.1-2 s) pulses of 6-10 V is presented which drastically improves the yield of nanopores that can be used for molecular recognition studies. In particular, this technique allows for sub-nanometer control over nanopore size under experimental conditions, facilitates complete wetting of nanopores, reduces noise by up to three orders of magnitude and rejuvenates used pores for further experimentation. This improvement in fabrication yield (over 90%) ultimately makes nanopore-based sensing more efficient, cost-effective and accessible. Tuning size using high electric fields facilitates nanopore fabrication and improves functionality for single-molecule experiments. Here, the use of nanopores for the detection of DNA-protein complexes is examined. As proof-of-concept, neutravidin bound to double-stranded DNA is used as a model complex. The creation of the DNA-neutravidin complex using polymerase chain reaction with biotinylated primers and subsequent purification and multiplex creation is discussed. Finally, an outlook for extending this scheme for the identification of proteins in a sample based on translocation signatures is presented which could be implemented in a portable lab-on-a-chip device for the rapid detection of disease biomarkers.

Multi-resolution analysis has been a very popular technique in the recent years. Wavelets have been used extensively to perform multi resolution image expansion and analysis. DCT, however, has been used to compress image but not for multi resolution image analysis. This thesis is an attempt to explore the possibilities of using DCT for multi-resolution image analysis. Naive implementation of block DCT for multi-resolution expansion has many difficulties that lead to signal distortion. One of the main causes of distortion is the blocking artifacts that appear when reconstructing images transformed by DCT. The new algorithm is based on line DCT which eliminates the need for block processing. The line DCT is one dimensional array based on cascading the image rows and columns in one transform operation. Several images have been used to test the algorithm at various resolution levels. The reconstruction mean square error rate is used as an indication to the success of the method. The proposed algorithm has also been tested against the traditional block DCT.

Image noise reduction, or denoising, is an active area of research, although many of the techniques cited in the literature mainly target additive white noise. With an emphasis on signal-dependent noise, this thesis presents the General Adaptive Monte Carlo Bayesian Image Denoising (GAMBID) algorithm, a model-free approach based on random sampling. Testing is conducted on synthetic images with two different signal-dependent noise types as well as on real synthetic aperture radar and ultrasound images. Results show that GAMBID can achieve state-of-the-art performance, but suffers from some limitations in dealing with textures and fine low-contrast features. These aspects can by addressed in future iterations when GAMBID is expanded to become a versatile denoising framework.

Denna uppsats syftar till att undersöka användbarheten av metoden Independent Component Analysis (ICA) för brusreducering av bilder tagna av infraröda kameror. Speciellt fokus ligger på att reducera additivt brus. Bruset delas upp i två delar, det Gaussiska bruset samt det sensorspecifika mönsterbruset. För att reducera det Gaussiska bruset används en populär metod kallad sparse code shrinkage som bygger på ICA. En ny metod, även den byggandes på ICA, utvecklas för att reducera mönsterbrus. För varje sensor utförs, i den nya metoden, en analys av bilddata för att manuellt identifiera typiska mönsterbruskomponenter. Dessa komponenter används därefter för att reducera mönsterbruset i bilder tagna av den aktuella sensorn. Det visas att metoderna ger goda resultat på infraröda bilder. Algoritmerna testas både på syntetiska såväl som på verkliga bilder och resultat presenteras och jämförs med andra algoritmer. / The purpose of this thesis is to evaluate the applicability of the method Independent Component Analysis (ICA) for noise reduction of infrared images. The focus lies on reducing the additive uncorrelated noise and the sensor specific additive Fixed Pattern Noise (FPN). The well known method sparse code shrinkage, in combination with ICA, is applied to reduce the uncorrelated noise degrading infrared images. The result is compared to an adaptive Wiener filter. A novel method, also based on ICA, for reducing FPN is developed. An independent component analysis is made on images from an infrared sensor and typical fixed pattern noise components are manually identified. The identified components are used to fast and effectively reduce the FPN in images taken by the specific sensor. It is shown that both the FPN reduction algorithm and the sparse code shrinkage method work well for infrared images. The algorithms are tested on synthetic as well as on real images and the performance is measured.

Image noise reduction, or denoising, is an active area of research, although many of the techniques cited in the literature mainly target additive white noise. With an emphasis on signal-dependent noise, this thesis presents the General Adaptive Monte Carlo Bayesian Image Denoising (GAMBID) algorithm, a model-free approach based on random sampling. Testing is conducted on synthetic images with two different signal-dependent noise types as well as on real synthetic aperture radar and ultrasound images. Results show that GAMBID can achieve state-of-the-art performance, but suffers from some limitations in dealing with textures and fine low-contrast features. These aspects can by addressed in future iterations when GAMBID is expanded to become a versatile denoising framework.

CRISP is a data acquisition and image reconstruction technique that offers theoretical increases in signal-to-noise ratio (SNR) and dynamic range over traditional methods in magnetic resonance imaging (MRI). The incoming broadband MRI signal is de-multiplexed into multiple narrow frequency bands using analog filters. Signal from each narrowband channel is then individually captured and digitized. The original signal is recovered by recombining all the channels via weighted addition, where the weights correspond to the frequency responses of each narrowband filter. With ideal bandpasses and bandwidth dependent noise after filtering, SNR increase is proportional to sqrt(N), where N is the number of bandpasses. In addition to SNR improvement, free induction decay (FID) echoes in CRISP experience a slower decay rate. In situations where resolution is limited by digitization noise, CRISP is able to capture data further out into the higher frequency regions of k-space, which leads to a relative increase in resolution. The conversion from one broadband MR signal into multiple narrowband channels is realized using a comb or bank of active analog bandpass filters. A custom CRISP RF receiver chain is implemented to downconvert and demodulate the raw MR signal prior to narrowband filtering, and to digitize the signals from each filter channel simultaneously. Results are presented demonstrating that the CRISP receiver chain can acquire 2D MR images (without narrowband filters) with SNR similar to SNR of images obtained with a clinical system. Acquiring 2D CRISP images (with narrowband filters) was not possible due to the lack of phase lock between rows in k-space. RMS noise of narrowband, broadband and unfiltered 1D echoes are compared.

Wavelet methods for image denoising have became widespread for the last decade. The effectiveness of this denoising scheme is influenced by many factors. Highlights can be listed as choosing of wavelet used, the threshold determination and transform level selection for thresholding. For threshold calculation one of the classical solutions is Wiener filter as a linear estimator. Another one is VisuShrink using global thresholding for nonlinear area. The purpose of this work is to develop a Java toolbox which is used to find best denoising schemes for distinct image types particularly Synthetic Aperture Radar (SAR) images. This can be accomplished by comparing these basic methods with well known data adaptive thresholding methods such as SureShrink, BayeShrink, Generalized Cross Validation and Hypothesis Testing. Some nonwavelet denoising process are also introduced. Along with simple mean and median filters, more statistically adaptive median, Lee, Kuan and Frost filtering techniques are also tested to assist wavelet based denoising scheme. All of these methods on the basis of wavelet models and some traditional methods will be implemented in pure java code using plug-in concept of ImageJ which is a popular image processing tool written in Java.

<p>In the era of VLSI the technological advancements have lead us to integrate not only digital circuits of high device density but both digital and analog circuits on to the same chip. In recent years the number of devices on a chip has spectacularly increased, all</p><p>because of the downward scaling in sizes of the devices. But because of this dramatic scaling the devices have become more sensitive to the power-ground noise. Now in designing a mix signal system within single silicon die that has high speed digital circuits</p><p>along with high performance analog circuits the digital switching noise becomes a foremost concern for the correct functioning of the system.</p><p>The purpose of the thesis is to evaluate the reduction of Simultaneous Switching Noise in analog signal band with in the chip. The experiment is done by the use of DCVSL circuits combined with a novel method of implementation, instead of the common static circuits in the core design. These DCVSL circuits have the property to draw periodic currents from the power supply. So if the circuit draws equal amount of current at each clock cycle independent of the input fed to it, the generated noise’s frequency content, produced due to current spikes will then be shifted above the input clock frequency.</p><p>The idea is to reduce Simultaneous Switching Noise (SSN) by half of the clock frequency in the frequency band. This frequency band often contains to the analog signal band of a digital-to-analog converter. To evaluate the method two pipelined adders have been implemented in 0.13 μm CMOS technology. The proposed method (test circuit) is</p><p>implemented using DCVSL techniques and the reference circuit using static CMOS logic. For testing of the design we generated the input data on-chip. The pseudo-random data is generated by implementing two different length PRBS. We have also implemented a ROM containing specific test patterns. In the end, we have achieved a 10 dB decrease of noise level at the substrate node on the chip.</p>

In the era of VLSI the technological advancements have lead us to integrate not only digital circuits of high device density but both digital and analog circuits on to the same chip. In recent years the number of devices on a chip has spectacularly increased, all because of the downward scaling in sizes of the devices. But because of this dramatic scaling the devices have become more sensitive to the power-ground noise. Now in designing a mix signal system within single silicon die that has high speed digital circuits along with high performance analog circuits the digital switching noise becomes a foremost concern for the correct functioning of the system. The purpose of the thesis is to evaluate the reduction of Simultaneous Switching Noise in analog signal band with in the chip. The experiment is done by the use of DCVSL circuits combined with a novel method of implementation, instead of the common static circuits in the core design. These DCVSL circuits have the property to draw periodic currents from the power supply. So if the circuit draws equal amount of current at each clock cycle independent of the input fed to it, the generated noise’s frequency content, produced due to current spikes will then be shifted above the input clock frequency. The idea is to reduce Simultaneous Switching Noise (SSN) by half of the clock frequency in the frequency band. This frequency band often contains to the analog signal band of a digital-to-analog converter. To evaluate the method two pipelined adders have been implemented in 0.13 μm CMOS technology. The proposed method (test circuit) is implemented using DCVSL techniques and the reference circuit using static CMOS logic. For testing of the design we generated the input data on-chip. The pseudo-random data is generated by implementing two different length PRBS. We have also implemented a ROM containing specific test patterns. In the end, we have achieved a 10 dB decrease of noise level at the substrate node on the chip.