In the field of communications, a high data rate and low multi-path fading is required for efficient information exchange. Orthogonal Frequency Division Multiplexing (OFDM) is a widely accepted IEEE 802.11n (and many others) standard for usage in communication systems operating in fading dispersive channels. In this thesis, we modeled the OFDM algorithm at the behavioral level in VHDL/Verilog that was successfully synthesized/verified on an FPGA. Due to rapid technology scaling, FPGAs have become popular and are low-cost and high performance alternatives to (semi-) custom ASICs. Further, due to reprogramming flexibility, FPGAs are useful in rapid prototyping. As per the IEEE standard, we implemented both transmitter and receiver with four modulation schemes (BPSK, QPSK, QAM16, and QAM64). We extensively verified the design in simulation as well as on Altera Stratix IV EP4SGX230KF40C2 FPGA (Terasic DE4 Development Board). The synthesized design ran at 100 MHz clock frequency incurring 54 µ sec. end-to-end latency and 8% logic utilization.