The aim of this thesis is to implement flexible interpolators and decimators onField Programmable Gate Array (FPGA). Interpolators and decimators of differentwordlengths (WL) are implemented in VHDL. The Farrow structure is usedfor the realization of the polyphase components of the interpolation/decimationfilters. A fixed set of subfilters and adjustable fractional-delay multiplier valuesof the Farrow structure give different linear-phase finite-length impulse response(FIR) lowpass filters. An FIR filter is designed in such a way that it can be implementedfor different wordlengths (8-bit, 12-bit, 16-bit). Fixed-point representationis used for representing the fractional-delay multiplier values in the Farrow structure. To perform the fixed-point operations in VHDL, a package called fixed pointpackage [1] is used. A 8-bit, 12-bit, and 16-bit interpolator are implemented and their performancesare verified. The designs are compiled in Quartus-II CAD tool for timing analysisand for logical registers usage. The designs are synthesised by selecting Cyclone IVGX family and EP4X30CF23C6 device. The wordlength issues while implementingthe interpolators and decimators are discussed. Truncation of bits is required inorder to reduce the output wordlength of the interpolator and decimator.

In the field of communications, a high data rate and low multi-path fading is required for efficient information exchange. Orthogonal Frequency Division Multiplexing (OFDM) is a widely accepted IEEE 802.11n (and many others) standard for usage in communication systems operating in fading dispersive channels. In this thesis, we modeled the OFDM algorithm at the behavioral level in VHDL/Verilog that was successfully synthesized/verified on an FPGA. Due to rapid technology scaling, FPGAs have become popular and are low-cost and high performance alternatives to (semi-) custom ASICs. Further, due to reprogramming flexibility, FPGAs are useful in rapid prototyping. As per the IEEE standard, we implemented both transmitter and receiver with four modulation schemes (BPSK, QPSK, QAM16, and QAM64). We extensively verified the design in simulation as well as on Altera Stratix IV EP4SGX230KF40C2 FPGA (Terasic DE4 Development Board). The synthesized design ran at 100 MHz clock frequency incurring 54 µ sec. end-to-end latency and 8% logic utilization.