<div>The availability of modern hardware with large amounts of memory created a shift in the development of data-centric software; from optimizing I/O operations to optimizing computation. As a result, the main challenge has become using the memory hierarchy (cache, RAM, distributed, etc) efficiently. In order to overcome this difficulty, programmers of data-centric programs need to use low-level APIs such as Pthreads or MPI to manually optimize their software because of the intrinsic difficulties and the low productivity of these APIs. Data-centric systems such as Apache Spark are becoming more and more popular. These kinds of systems offer a much simpler interface and allow programmers and scientists to write in a few lines what would have been thousands of lines of low-level MPI code. The core benefit of these systems comes from the introduction of deferred APIs; the code written by the programmer is actually building a graph representation of the computation that has to be executed. This graph can then be optimized and compiled to achieve higher performance.</div><div><br></div><div>In this dissertation, we analyze the limitations of current data-centric systems such as Apache Spark, on relational and heterogeneous workloads interacting with machine learning frameworks. We show that the compilation of queries in multiples stages and the interfacing with external systems is a key impediment to performance because of their inability to optimize across code boundaries. We present Flare, an accelerator for data-centric software, which provides performance comparable to the state of the art relational systems while keeping the expressiveness of high-level deferred APIs. Flare displays order of magnitude speed up on programs combining relational processing and machine learning frameworks such as TensorFlow. We look at the impact of compilation on short-running jobs and propose an on-stack-replacement mechanism for generative programming to decrease the overhead introduced by the compilation step. We show that this mechanism can also be used in a more generic way within source-to-source compilers. We develop a new kind of static analysis that allows the reverse engineering of legacy codes in order to optimize them with Flare. The novelty of the analysis is also useful for more generic problems such as formal verification of programs using dynamic allocation. We have implemented a prototype that successfully verifies programs within the SV-COMP benchmark suite.</div>

La tendance du secteur automobile à développer des capteurs etactionneurs intelligents, faire cohabiter l’électronique analogique et l’électroniquenumérique devient un art. Placé au sein des actionneurs, pour la sécurité et le confortdes passagers, les convertisseurs analogique-numérique (CAN) sont les composantsclés de ces systèmes intelligents. Un CAN rapide, précis, et peu cher serévèle être un précieux allié pour les équipementiers automobiles. Pour diminuerles coûts, et faciliter l’utilisation de ce bloc, la surface de silicium occupée doit êtreconsidérablement réduite à moins de 0.5mm2. Quant à la précision du convertisseur,12-bits tous les 5 coups d’une horloge de 100 MHz sont nécessaires pour unetempérature de -40°C à 175°C.Ce travail de recherche se focalise sur l’amélioration de l’efficacité énergétiquesous les contraintes que l’environnement automobile représente. Notre principalecontribution réside dans le développement par une approche top-downd’une nouvelle architecture à 3 étages de topologies différentes. Le premier étageest un ΣΔ-Incrémental intrinsèquement linéaire. Le second étage est un algorithmiquepour augmenter rapidement la résolution. Enfin, un SAR accroît la résolutionavec faible consommation de puissance et surface de silicium.Suite à l’analyse de 40 années d’état de l’art, la nouvelle architecture proposéefut validée par vérification des non-linéarités statiques (DNL, INL) à différentsniveaux de modélisation. Commençant par un modèle MATLAB sans leslimitations analogiques, le niveau de modélisation se raffine petit à petit jusqu’auniveau transistor du convertisseur. Un modèle Verilog-A permit la déterminationdes spécifications minimales des briques de base analogiques: les comparateurs etles amplificateurs à transconductance. La sensibilité de ces derniers à la températurefut analysée pour limiter les erreurs commises sur les tensions analogiques.Une fois dessinés et les parasites extraits, les modèles variant avec la températureremplacent leurmodèle Verilog-A respectif afin d’obtenir les performances finales.Parallèlement, deux architectures de comparateurs ont été évaluées en températureau sein d’une première puce de test. Deux méthodes ont été utilisées pour estimerl’offset des comparateurs, et un nouveau circuit asynchrone estime le délai.Une seconde puce de test permet de vérifier la sensibilité du SAR à la températuremalgré un fonctionnement pseudo-asynchrone.Pour les comparateurs, le nouveau circuit de mesure différentielle du retardmontre une précision de 60 ps dans le pire des cas, pour la plus petite surface surpuce connue en considérant la technologie utilisée. Comme la variation du retardest dépendante de la température, le choix d’un Strong-ARM (SA) ou d’un Double-Tail (DT) dépendra du bruit, de la puissance, de la tension d’alimentation, et de laspécification de kickback. Pour une tension d’alimentation standard, les SA comparateursciblent les systèmes à faible consommation avec une tolérance élevéepour le kickback différentiel. Au contraire, les DT comparateurs acceptent uneplage de tension d’alimentation plus faible, et présentent un faible kickback différentiel,mais un bruit plus important. Testé de -40°C à 200°C, le dernier étagedu CAN proposé, n’a pas besoin d’être calibré jusqu’à 180°C. Les résultats encourageantssur cet étage permettent la réutilisation de celui-ci pour calibrer les étagesprécédents. Et pour le CAN, nous estimons une résolution possible de 11,2 bitsen 5 cycles d’horloge par échantillon avec une extension à 13,3 bits en 6 cyclesd’horloge. La surface estimée est de 0,12mm2.La puce de test pour le CAN est en cours de finalisation, une première étapesera sa caractérisation. Les résultats de cette session de mesure détermineront s’ilest possible de pousser l’architecture à des fréquences plus élevées pour ensuitetirer parti du traitement numérique pour conserver les performances. / In the automotive industry, the trend being to develop smartsensors and actuators, the on-board electronic has been ever more an artful workto combine analog electronics and the digital one. While many monitoring andcontrol systems play a crucial role as well for the safety as for the comfort of passengers,small components, like ADCs, are mandatory as a building block or as anessential functionality integrated into smart actuators. To that extent, a low-cost,fast and accurate analog to digital converter operating in those harsh conditionsis a good ally for equipment manufacturers. To decrease the cost, the area is ofprimary concern. Considering re-use of the ADC as an IP-bloc, the area has beenlimited to less than half a square millimeter for an low-oversampling ratio of 5 tooutput a 12-bit code at a sample rate of 20 MSamples/s, over a wide temperaturerange from-40°C to 175°C.This work focuses on the design of high-precision, high-speed and energyefficient ADC under the harsh environment the automotive one represents. Ourmain contribution relies on the development of an new hybrid topology proposalusing 3 stages to cope with such constraints based on a top-down approach: A firstcounting stage inherently linear, an algorithmic stage allowing to increase rapidlythe precision, and a SAR stage, ideal in terms of area and consumption, for a lownumber of bits.Based on a 40 years literature review, a new topology proposal has been validatedby checking its static metric of non-linearity (DNL, INL) at different level ofmodelisation. Starting by a MATLAB implementation without analog limitations,we refined step by step the model tillwe reach a transistor level of the ADC. Thence,Verilog-A model allows us to fix the minimum requirements of the key analog buildingblocks, to wit comparators and OTA. The latter has been analysed in order tolimit the settling error sensitivity to the temperature. Laid-out, parasitic extractedsimulation results of these considering PVT variations, they replace then previoushigh-level model to give final performances. Meanwhile, two well-known comparatorarchitectures have been assessed as IP blocs inside a first test chip. To performthe offset extraction, both a conventional and a feedback loop have been inspected.To assess, the delay a new asynchronous circuit has been proposed. A secondchip tests the sensitivity of the SAR to validate both the pseudo-asynchronousdigital scheme, and a Double-Tail comparator in real operating conditions.For comparators, the new differential measurement circuit of the delaydemonstrate an accuracy of 60 ps in the worst case, over a large temperature rangefor the smallest chip area known with respect to the technology node size. Thetemperature variation of the delay being temperature dependent, the choice of aStrong-ARM or a Double-Tail hinge on the noise, power, supply voltage, and kickbackspecification. For standard power supply voltage, the Strong-ARM latch targetslow-power systems application with a high tolerance for differential kickback.To the contrary, a Double-Tail latch allows lower power supply voltage range, withlow-differential kickback. Otherwise, the Double-Tail exhibit a higher noise due tothe integration in its first stage. Tested from -40°C to 200°C, the last stage of theproposed ADC topology does not need calibration up to 180°C. The encouragingresults on this stage allows the re-use of the SAR to calibrate the previous stages.And considering the ADC, we estimate a possible resolution of 11.2-bits in 5 clockcycles per sample with an extension to 13.3-bits in 6 clock cycles with an estimatedarea of 0.12 mm2.The ADC test chip not being fabricated yet, a first step is the characterizationof the ADC. From the results of the planned measurement session, the maingoal is to push the architecture at higher sampling rates to then leverage the digitalprocessing to enhance the sampling rate without changing the analog.

To understand animal behaviour, it is important to consider the environment in which it occurs. The environment, consisting of both abiotic factors and social context, is usually highly variable and leads to variation in individual’s and group’s behaviour. To better understand the environmental influences on behaviour of pygmy halfbeaks (Dermogenys collettei), a small live-bearing fish, I viewed videos of shoals of wild halfbeaks in Singapore. I investigated effects of environmental variation (water depth, canopy cover and water vegetation) and social environment (group size and male to female sex ratio) on halfbeaks’ aggression and mating behaviours. I found that environment had little effect and most variation between studied shoals was probably due to social factors. I found some evidence for aggression increase in larger shoals, primarily in males. Sex ratio had different relation with aggression for individual sexes and mating behaviours decreased when sex ratio became more male biased. This study shows that halfbeaks probably modify their behaviour in relation to social environment. I also show that these changes are similar to those described in other species, which strengthens the validity of using halfbeaks to study social interactions.

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Competition over access for mates has led to the evolution of many striking examples of morphological traits and behaviour in animals. The rapid development of the sexual selection field in recent decades have dramatically advanced our understanding of what traits make individuals more successful in attracting mates and how preferences for mates evolve over time. However, till now, research in this field has put less emphasis on the mechanisms that underlie variation in mate choice and sexual behaviour. Cognitive processes could potentially be key drivers of individual variation in mating preferences and sexual behaviours and therefore deserve further investigation. In this thesis, I used guppies artificially selected for relative brain size as the model system to study the association between brain size, cognitive ability and various aspects of mate choice. Previous studies in this model system showed that large-brained individuals of both sexes outperformed small-brained individuals in cognitive tests. Here I quantified their sexual behaviours and mating preferences to provide novel empirical data concerning the association between brain size, cognitive ability and sexual selection. In dichotomous choice preference tests based on visual cues, comparisons between large-brained and small-brained guppies showed important differences in their assessment of mate quality. These results are not driven by pre-existing visual biases caused by the artificial selection since further investigation of the visual capacity of these fish detected no differences between large-brained and small-brained individuals in their sensitivity to colour or in their capacity to resolve spatial detail. I also quantified sexual behaviour in male guppies artificially selected for relative brain size and found no difference in the behaviours of large-brained and small-brained males in a single male-single female non-competitive scenario. On the contrary, in a more complex social setting I found a reduction in large-brained males in the rate of courtship towards females and dominance displays towards other males when exposed to different degrees of predation threat and different numbers of male competitors. However, this reduction in behavioural intensity did not result in a lower access to copulation with females for large-brained males. I likewise evaluated female sexual behaviour and found that large-brained females had higher behavioural flexibility such that they decreased their receptiveness towards males more strongly under higher levels of predation threat. Together, these results provide novel empirical evidence that brain size and cognitive ability are tightly linked to mating preferences and sexual behaviours. These findings suggest that brain size and cognitive ability might be important mechanisms behind variation in mating preferences and in sexually selected traits across and within species. / <p>At the time of the doctoral defense, the following papers were unpublished and had a status as follows: Paper 2: Manuscript. Paper 3: Manuscript. Paper 5: Manuscript.</p>