The project deals with the testing of SRAM memories using method MBIST with the utilisation of sofware tool Tessent Memory BIST. The main purpose is to get familiar with memory testing and to create a design for testing on a specific chip which after its implementation on the chip will retain the original features and functions. Subsequently, the tool is evaluated on its usability.

Cette thèse aborde le problème de la synchronisation globale de grand système sur puce (SoC). Il est centré sur l'étude d'une technique de remplacement de la distribution d'horloge classique et d'une communication asynchrone. Il permet la mise en œuvre de circuit synchrone très fiable. Mon projet de thèse vise à étudier et mettre en œuvre un vaste réseau (10x10) de boucle à verrouillage de phase tous numérique (ADPLL), contenant 100 nœuds générant une horloge pour chaque circuit numérique local. Le prototype a été réalisé sur les horloges de génération de silicium dans la gamme de 903-1161 MHz. Elle met en évidence une erreur de phase maximale de moins de 40 ps entre deux horloges dans toutes les zones voisines. Un autre résultat important est l'analyse de l'erreur de phase entre les deux oscillateurs non-voisins dans la distance. En étudiant un prototype FPGA du réseau, on a obtenu que l'erreur de phase maximale à l'état d'équilibre entre un signal d'horloge et le signal de référence est inférieur à trois étapes des étapes de quantification PFD. Afin de valider les performances de la synchronisation dans ASIC, nous avons conçu un circuit d'une erreur de mesure sur la puce d'horloge. Ce circuit a un taux faible de la lecture hors puce (quelques MHz), et une résolution élevée (+ -2,5 ps). Reconfiguration constitue une autre caractéristique intéressante. Nous avons exploré cette fonction et a proposé une nouvelle topologie avec des configurations différentes pour les nœuds sur la frontière et dans le noyau du réseau. Cette topologie présente un avantage en interdisant la propagation des erreurs de phase et de réflexion. / This thesis addresses the problem of global synchronization of large system on chip (SoC). It focuses on the study of an alternative clock generation technique to conventional clock distribution and asynchronous communication. It allows implementation of highly reliable synchronous circuit. My PhD project aims to study and implement a large network (10x10) of all digital phase-locked loop (ADPLL), containing 100 nodes generating a clock for each local digital circuitry. The prototype was implemented on silicon generating clocks in the range 903-1161 MHz. It highlights a maximum phase error of less than 40 ps between two clocks in any neighboring zones. Another important result is the analysis of phase error between two non-neighboring oscillators in distance. By studying an FPGA prototype of the network, we obtained that maximum phase error at steady state between any clock signal and the reference signal is less than three steps of the PFD quantification steps. In order to validate the performance of synchronization in ASIC, we designed an on-chip clocking error measurement circuit. This circuit has a low rate for the off-chip readout (several MHz), and a high resolution (+-2.5 ps). Reconfigurability is another attractive feature. We have explored this feature and proposed a novel topology with different configurations for nodes on the border and in the kernel of the network. This topology has an advantage in prohibiting phase error propagation and reflection.

Power dissipated during scan testing is becoming increasingly important for today’s very complex sequential circuits. It is shown that the power dissipated during test mode operation is in general higher than the power dissipated during functional mode operation, the test mode average power may sometimes go upto 3x and the peak power may sometimes go upto 30x of normal mode operation. The power dissipated during the scan operation is primarily due to the switching activity that arises in scan cells during the shift and capture operation. The switching in scan cells propagates to the combinational block of the circuit during scan operation, which in turn creates many transition in the circuit and hence it causes higher dynamic power dissipation. The excessive average power dissipated during scan operation causes circuit damage due to higher temperature and the excessive peak power causes yield loss due to IR-drop and cross talk. The higher peak power also causes the thermal related issue if it last for sufficiently large number of cycles. Hence, to avoid all these issues it is very important to reduce the peak power during scan testing. Further, in case of multi-module SoC testing the reduction in peak power facilitates in reducing the test application time by scheduling many test sessions parallelly. In this dissertation we have addressed all the above stated issues. We have proposed three different techniques to deal with the excessive peak power dissipation problem during test. The first solution proposes an efficient graph theoretic methodology for test vector reordering to achieve minimum peak power supported by the given test vector set. Three graph theoretic problems are formulated and corresponding algorithms to solve the problems are proposed. The proposed methodology also minimizes average power for the given minimum peak power. Further, a lower bound on minimum achievable peak power for a given test set is defined. The results on several benchmarks show that the proposed methodology is able to reduce peak power significantly. To address the peak power problem during scan test-cycle (the cycle between launch and capture pulse) we have proposed a scan chain reordering technique. A new formulation for scan chain reordering as TSP (Traveling Sales Person) problem and a solution is proposed. The experimental results show that the proposed methodology is able to minimize considerable amount of peak power compared to the earlier proposals. The capture power (power dissipated during capture cycle) problem in testing multi chip module (MCM) is also addressed. We have proposed a methodology to schedule the test set to reduce capture power. The scheduling algorithm consist of reordering of test vector and insertion of idle cycle to prevent capture cycle coincidence of scheduled cores. The experimental results show the significant reduction in capture power without increase in test application time.