Standard methodologies exist for testing and characterizing digital circuits but the same cannot be said of analog circuits. Though much theoretical work has been done to model the linear and nonlinear aspects of analog circuits, a firm practical background for the design of testable analog cells has yet to be set. The industry largely looks for solutions wherein some form of built in self-test (BIST) can be incorporated into the analog circuits to make the testing at the manufacturing level easy and accurate. Since the testers in the industry are generally digital, test circuits that use logic levels at the output to make measurements are attractive. This thesis examines the design of such test circuits for one specific analog circuit, the opamp. Test circuits to measure the gain, gain-bandwidth product, phase response and the slew rate of the opamp have been designed and experimental results are presented. The main advantages of these tests are that they are simple, fast, accurate and easy to incorporate in an integrated circuit. / Graduation date: 1994

The feasibility of developing test circuits to perform in-circuit testing of analog circuits is investigated in this thesis. A modular approach to analog testing has been adopted. Accordingly, the testing of an operational amplifier, which is a basic building block in analog circuits, is addressed. One convenient technique for measuring the frequency response of an op-amp requires a unity gain buffer to be inserted into its feedback loop. This buffer has to be simple in construction, small and accurate. Two buffer circuits that satisfy these requirements are described in this thesis. Enhanced slewing techniques are devised to achieve increased levels of performance. The buffers were integrated with an op-amp into a test chip. Digital logic is used to provide controllability and accessibility to each of the buffers and the op-amp so that they can characterized separately. The performance of the enhanced slewing buffers was verified with measurements performed on the test chip. The performance of the buffers conformed well with the simulated values. The buffers exhibited excellent settling times even while driving large capacitive loads. Their output swing and distortion performance were good for inputs as large as 2 V peak-to-peak values. / Graduation date: 1994