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High frequency techniques for advanced MOS device characterizationWang, Yun, January 2008 (has links)
Thesis (Ph. D.)--Rutgers University, 2008. / "Graduate Program in Electrical and Computer Engineering." Includes bibliographical references (p. 189-201).
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Automatic layout generation of static CMOS combinational cells and blocks /Guan, Bingzhong. January 1996 (has links)
Thesis (Ph. D.)--University of Washington, 1996. / Vita. Includes bibliographical references (leaves [127]-133).
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Some experimental studies of neutron irradiation and beryllium implantation induced defects in 6H-SiCChen, Xudong. January 2001 (has links)
Thesis (Ph.D.)--University of Hong Kong, 2002. / Includes bibliographical references (leaves 102-108) Also available in print.
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A timing macro model for performance optimization of CMOS logic circuits.Shum, Roger Chi Fai, Carleton University. Dissertation. Engineering, Electrical. January 1992 (has links)
Thesis (M. Eng.)--Carleton University, 1992. / Also available in electronic format on the Internet.
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Technology mapping algorithms for CMOS dynamic logic circuits.Ramirez Ortiz, Rolando, Carleton University. Dissertation. Engineering, Electrical. January 1992 (has links)
Thesis (M. Eng.)--Carleton University, 1992. / Also available in electronic format on the Internet.
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Efficient image compression system using a CMOS transform imagerLee, Jungwon. January 2009 (has links)
Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010. / Committee Chair: Anderson, David; Committee Member: Dorsey, John; Committee Member: Hasler, Paul; Committee Member: Kang, Sung Ha; Committee Member: Romberg, Justin. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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<>.Bien, Franklin Young-Jae. January 2006 (has links)
Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2006. / Joy Laskar, Committee Chair ; Manos Tentzeris, Committee Member ; Kevin Kornegay, Committee Member ; Nikil Jayant, Committee Member ; Jianmin Qu, Committee Member. Non-Latin script record
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Process costing of microchipGajera, Dipesh. January 2006 (has links)
Thesis (M.S.)--West Virginia University, 2006. / Title from document title page. Document formatted into pages; contains vii, 92 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 85-91).
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Investigation of theoretical limitations of recombination DCIV methodology for characterization of MOS transistorsChen, Zuhui. January 2005 (has links)
Thesis (Ph. D.)--University of Florida, 2005. / Title from title page of source document. Document formatted into pages; contains 166 pages. Includes vita. Includes bibliographical references.
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Development of a deep-submicron CMOS process for fabrication of high performance 0.25 um [micron] transistors /Aquilino, Michael V. January 2006 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 2006. / Typescript. Includes bibliographical references (leaves 144-146).
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