by Kei-Fu Mak. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1995. / Includes bibliographical references (leaves 103-108). / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Flynn's Classification --- p.1 / Chapter 1.2 --- Parallel Computation Approaches --- p.2 / Chapter 1.3 --- Architecture Issues --- p.2 / Chapter 1.4 --- Communications --- p.3 / Chapter 1.5 --- Object Oriented Models --- p.4 / Chapter 1.6 --- Parallel Objects --- p.5 / Chapter 1.7 --- Related Works --- p.6 / Chapter 1.7.1 --- Actor Model --- p.6 / Chapter 1.7.2 --- Nested Object --- p.7 / Chapter 1.7.3 --- Nested Transaction --- p.7 / Chapter 1.7.4 --- C++* --- p.8 / Chapter 1.8 --- Summary --- p.8 / Chapter 2 --- Design Issues --- p.10 / Chapter 2.1 --- Goals --- p.11 / Chapter 2.1.1 --- Parallel Model --- p.11 / Chapter 2.1.2 --- Portability --- p.11 / Chapter 2.1.3 --- Class Extension --- p.12 / Chapter 2.2 --- Arguments --- p.12 / Chapter 2.2.1 --- Single versus Multiple Thread Objects --- p.12 / Chapter 2.2.2 --- Active versus Passive Objects --- p.13 / Chapter 2.2.3 --- Synchronous versus Asynchronous Communications --- p.13 / Chapter 2.2.4 --- Architecture Dependence versus Independence --- p.13 / Chapter 2.3 --- Class Structure --- p.14 / Chapter 2.3.1 --- Kernel Class --- p.14 / Chapter 2.3.2 --- Concurrent Class --- p.15 / Chapter 2.3.3 --- Share Class --- p.15 / Chapter 3 --- Execution Model --- p.17 / Chapter 3.1 --- Parallel Objects --- p.19 / Chapter 3.1.1 --- Initialization Phase --- p.19 / Chapter 3.1.2 --- Communication System --- p.21 / Chapter 3.1.3 --- Phase Transition --- p.22 / Chapter 3.1.4 --- Outstanding Requests --- p.24 / Chapter 3.2 --- Concurrent Object --- p.25 / Chapter 3.2.1 --- Service Methods --- p.26 / Chapter 3.2.2 --- Immutable Methods --- p.26 / Chapter 3.2.3 --- Urgent Methods --- p.27 / Chapter 3.2.4 --- Phase Transitional Methods --- p.28 / Chapter 3.2.5 --- Phase Immutable Methods --- p.29 / Chapter 3.3 --- Share Object --- p.30 / Chapter 3.3.1 --- Concurrency Control --- p.31 / Chapter 3.3.2 --- Ticket System --- p.33 / Chapter 3.4 --- Summary --- p.34 / Chapter 4 --- Kernel and Implementation --- p.37 / Chapter 4.1 --- Kernel Components --- p.37 / Chapter 4.1.1 --- Functionality --- p.38 / Chapter 4.1.2 --- Kernel Structure --- p.42 / Chapter 4.1.3 --- Kernel Interface --- p.43 / Chapter 4.1.4 --- Kernel Composition --- p.44 / Chapter 4.2 --- Implementation Issues --- p.46 / Chapter 4.2.1 --- Precompiler --- p.46 / Chapter 4.2.2 --- Object Manager --- p.49 / Chapter 4.2.3 --- Communication System --- p.51 / Chapter 4.2.4 --- Method Invocation --- p.52 / Chapter 4.2.5 --- Restrictions --- p.55 / Chapter 4.3 --- Summary --- p.55 / Chapter 5 --- Evaluation --- p.58 / Chapter 5.1 --- Case Study I --- p.58 / Chapter 5.2 --- Case Study II --- p.63 / Chapter 5.3 --- Overall Evaluation --- p.66 / Chapter 5.4 --- Summary --- p.70 / Chapter 6 --- Conclusion --- p.72 / Chapter A --- ACCEL Header Files --- p.78 / Chapter A.1 --- OBJID.H --- p.78 / Chapter A.2 --- OBJKERN.H --- p.80 / Chapter A.3 --- OBJCONC.H --- p.83 / Chapter A.4 --- OBJSHARE.H --- p.84 / Chapter B --- Case Studies --- p.87 / Chapter B.1 --- Gaussian Elimination --- p.87 / Chapter B.2 --- One Open End Tube --- p.96 / Bibliography --- p.103

Lau, Wai Shing. / Thesis submitted in: November 2006. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 85-94). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Field Programmable Gate Arrays --- p.2 / Chapter 1.2 --- FPGA technology mapping problem --- p.3 / Chapter 1.3 --- Motivations --- p.5 / Chapter 1.4 --- Contributions --- p.6 / Chapter 1.5 --- Thesis Organization --- p.9 / Chapter 2 --- Background Study --- p.11 / Chapter 2.1 --- Deterministic approach to technology mapping problem --- p.11 / Chapter 2.1.1 --- FlowMap --- p.12 / Chapter 2.1.2 --- DAOMap --- p.14 / Chapter 2.2 --- Stochastic approach --- p.15 / Chapter 2.2.1 --- Bio-Inspired Methods for Multi-Level Combinational Logic Circuit Design --- p.15 / Chapter 2.2.2 --- A Survey of Combinational Logic Circuit Representations in stochastic algorithms --- p.17 / Chapter 2.3 --- Genetic Parallel Programming --- p.20 / Chapter 2.3.1 --- Accelerating Phenomenon --- p.22 / Chapter 2.4 --- Chapter Summary --- p.23 / Chapter 3 --- A GPP based Logic Circuit Synthesizer --- p.24 / Chapter 3.1 --- Overall system architecture --- p.25 / Chapter 3.2 --- Multi-Logic-Unit Processor --- p.26 / Chapter 3.3 --- The Genotype of a MLP program --- p.28 / Chapter 3.4 --- The Phenotype of a MLP program --- p.31 / Chapter 3.5 --- The Evolution Engine --- p.33 / Chapter 3.5.1 --- The Dual-Phase Approach --- p.33 / Chapter 3.5.2 --- Genetic operators --- p.35 / Chapter 3.6 --- Chapter Summary --- p.38 / Chapter 4 --- MLP in hardware --- p.39 / Chapter 4.1 --- Motivation --- p.39 / Chapter 4.2 --- Hardware Design and Implementation --- p.40 / Chapter 4.3 --- Experimental Settings --- p.43 / Chapter 4.4 --- Experimental Results and Evaluations --- p.46 / Chapter 4.5 --- Chapter Summary --- p.50 / Chapter 5 --- Feasibility Study of Multi MLPs --- p.51 / Chapter 5.1 --- Motivation --- p.52 / Chapter 5.2 --- Overall Architecture --- p.53 / Chapter 5.3 --- Experimental settings --- p.55 / Chapter 5.4 --- Experimental results and evaluations --- p.59 / Chapter 5.5 --- Chapter Summary --- p.59 / Chapter 6 --- A Hybridized GPPLCS --- p.61 / Chapter 6.1 --- Motivation --- p.62 / Chapter 6.2 --- Overall system architecture --- p.62 / Chapter 6.3 --- Experimental settings --- p.64 / Chapter 6.4 --- Experimental results and evaluations --- p.66 / Chapter 6.5 --- Chapter Summary --- p.70 / Chapter 7 --- A Memetic GPPLCS --- p.71 / Chapter 7.1 --- Motivation --- p.72 / Chapter 7.2 --- Overall system architecture --- p.72 / Chapter 7.3 --- Experimental settings --- p.76 / Chapter 7.4 --- Experimental results and evaluations --- p.77 / Chapter 7.5 --- Chapter Summary --- p.80 / Chapter 8 --- Conclusion --- p.82 / Chapter 8.1 --- Future work --- p.83 / Bibliography --- p.85

A paradigm is presented for the parallelization of coarse-grain engineering and scientific applications. The coordination framework provides structure and an organizational strategy for a parallel solution in a distributed environment. Three categories of primitives which define the coordination framework are presented: structural, transformational. and operational. The prototype of the paradigm presented in this thesis is the first step towards a programming development tool. This tool will allow non-specialist programmers to parallelize existing sequential solutions through the distribution, synchronization and collection of tasks. The distributed control, multidimensional pipeline characteristics of the paradigm provide advantages which include load balancing through the use of self-directed workers, a simplified communication scheme ideally suited for infrequent task interaction, a simple programmer interface, and the ability of the programmer to use already existing code. Results for the parallelization of SPICE3Cl in a distributed system of fifteen SUN 3 workstations with one fileserver demonstrate linear speedup with slopes ranging from 0.7 to 0.9. A high-level abstraction of the system is presented in the form of a closed, single class, queuing network model. Using the Mean Value Analysis solution technique from queuing network theory, an expression for total execution time is obtained and is shown to be consistent with the well known Amdahl's Law. Our expression is in fact a refinement of Amdahl's Law which realistically captures the limitations of the system. We show that the portion of time spent executing serial code which cannot be enhanced by parallelization is a function of N, the number of workers in the system. Experiments reveal the critical nature of the communication scheme and the synchronization of the paradigm. Investigation of the synchronization center indicates that as N increases, visitations to the center increase and degrade system performance. Experimental data provides the information needed to characterize the impact of visitations on the perfoimance of the system. This characterization provides a mechanism for optimizing the speedup of an application. It is shown that the model replicates the system as well as predicts speedup over an extended range of processors, task count, and task size.

The goal of parallel processing is to achieve high speed computing by partitioning a program into concurrent parts, assigning them in an efficient way to the available processors, scheduling the program and then executing the concurrent parts simultaneously. In the past researchers have combined the allocation of tasks in a program and scheduling of those tasks into one operation. We define scheduling as a process of efficiently assigning priorities to the already allocated tasks in a program. Assignment of priorities is important in cases when more than one task at a processor is ready for execution. Most heuristics for scheduling consider certain parameters of the architecture and the program. These parameters could be the execution time of each operation in a program, the number of processors, etc. The impact of ignoring interprocessor communication (IPC) when ordering parallel tasks has, however, not been well studied.

Processed. Bibliography: leaves 123-124.

Bibliography: leaves [238]-244.

Thesis (Ph. D.)--Ohio State University, 2006. / Title from first page of PDF file. Includes bibliographical references (p. 161-168).

Multi-threaded applications are needed to realize the full potential of new chip-multi-threaded machines. Such applications are very difficult to program and orchestrate correctly, and transactional memory has been proposed as a way of alleviating some of the programming difficulties. However, transactional memory can directly be applied only to critical sections, while conditional synchronization remains difficult to implement correctly and efficiently. This dissertation describes EasySync, a simple and inexpensive extension to transactional memory that allows arbitrary conditional synchronization to be expressed in a simple and composable way. Transactional memory eliminates the need to use locks and provides composability for critical sections: atomicity of a transaction is guaranteed regardless of how other code is written. EasySync provides the same benefits for conditional synchronizations: it eliminates the need to use conditional variables, and it guarantees wakeup of the waiting transaction when the real condition it is waiting for is satisfied, regardless of whether other code correctly signals that change. EasySync also allows transactional memory systems to efficiently provide lock-free and condition variable-free conditional critical regions and even more advanced synchronization primitives, such as guarded execution with arbitrary conditional or guard code. Because EasySync informs the hardware the that a thread is waiting, it allows simple and effective optimizations, such as stopping the execution of a thread until there is a change in the condition it is waiting for. Like transactional memory, EasySync is backward compatible with existing code, which we confirm by running unmodified Splash-2 applications linked with an EasySync-based synchronization library. We also re-write some of the synchronization in three Splash-2 applications, to take advantage of better code readability, and to replace spin-waiting with its more efficient EasySync equivalents. Our experimental evaluation shows that EasySync successfully eliminates processor activity while waiting, reducing the number of executed instructions by 8.6% on average in a 16-processor CMP. We also show that these savings increase with the number of processors, and also for applications written for transactional memory systems. Finally, EasySync imposes virtually no performance overheads, and can in fact improve performance.

Thesis (M.S.)--Mississippi State University. Department of Computational Engineering. / Title from title screen. Includes bibliographical references.

Thesis (Ph. D.)--University of Oregon, 2001. / Typescript. Includes vita and abstract. Includes bibliographical references (leaves 141-156). Also available for download via the World Wide Web; free to University of Oregon users.