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A generic object-oriented simulation platform is developed in order to conduct experiments on the performance of assignment schemes. The simulation platform, called Genesis, is generic in the sense that it can model the key parameters that describe a parallel system: the architecture, the program, the assignment scheme and the message routing strategy. Genesis uses as its basis a sound architectural representation scheme developed in the thesis. The thesis reports results from a number of experiments assessing the performance of assignment schemes using Genesis. The comparison results indicate that the new assignment scheme proposed in this thesis is a promising alternative to the work-greedy assignment schemes. The proposed scheme has a time-complexity less than those of the work-greedy schemes and achieves an average performance better than, or comparable to, those of the work-greedy schemes. To generate an assignment, some parameters describing the program model will be required. In many cases, accurate estimation of these parameters is hard. It is thought that inaccuracies in the estimation would lead to poor assignments. The thesis investigates this speculation and presents experimental evidence that shows such inaccuracies do not greatly affect the quality of the assignments.

An 8 bit microcontroller slave unit was designed, constructed, and tested to demonstrate advantages and feasibility of master/slave parallel processing using conventional processors and relatively slow inter-processor communications. An 8 bit ISA bus controlled by an 80X86 is interfaced to a logic block that controls data flow to and from the slave processors. The slave processors retrieve tasks sent by the master processor and once completed, return results to the master that are buffered for the master's retrieval. The task message sent to the slave processors has task description and task parameters. The master has access to the bi-directional buffer and a status byte for each slave processor. Considerable effort is made to allow the hardware and software architecture to be expandable such that the general design could be used on different master/slave targets. Attention is also given to cost effective solutions such that development and possible market production can be considered. / Graduation date: 1999

Banyan networks comprise a large class of networks that have been used for interconnection in large-scale multiprocessors and telephone switching systems. Regular variants of Banyan networks, such as delta and butterfly networks, have been used in multiprocessors such as the IBM RP3 and the BBN Butterfly. Analysis of the performance of Banyan networks has typically focused on these regular variants. We present a methodology for performance analysis of unbuffered Banyan multistage interconnection networks. The methodology has two novel features: it allows analysis of networks where some inputs are more likely to be active than others, and allows analysis of Banyan networks of arbitrary topology.

M.S. / Computer Science & Engineering / A study was made of some of the characteristics, capabilities, and limitations of the iPSC concurrent computer manufactured by the Intel Corporation. Initial experiments with test programs measured the large amount of time required to send and receive messages between nodes and between the cube manager and the nodes. Programs adapted to run concurrently will have the greatest speedup over the same program executed serially if the computational time is large relative to the time spent passing messages. A large-scale computational chemistry program (named ECEPP83) that calculates the global minimum energy of peptide structures (a peptide is a small protein) was ported and adapted to execute on the iPSC computer. The data entry and checking portion of the original code was ported to the 286/310 Intel computer that serves as a manager of the 32 to 128 CPU's (nodes) of the iPSC. The data for each structure is sent by the manager to a separate node which reports its results back to the host or system manager and then is assigned another structure. This adaptation is able to concurrently minimize the energy for 32 chemical structures a maximum of approximately 17 times faster than the same data can be utilized serially on a VAX 11-780 computer. A user manual was written to assist the user in assembling the input data file.

This thesis is concerned with architecture for long term general purpose computers. The work is based on current trends in machine architecture and technology. Projections from these generated "Architectural Soups". An Architectural Soup has the potential to emulate many different machine architectures. The characteristics of this class of machine are, three dimensional, simple cells and a simple communications topology, which can be reconfigured at a very low level. This thesis aims to show potential usefulness and viability of machines with such capability. Methods of programming are considered, and important design issues are investigated. A specific implementation architecture is described and illustrated through simulation. An assessment is made of the architecture and of the simulator used. In addition, the implementation architecture is used as the basis for a VLSI design, which shows the simplicity of a Soup cell, and provides estimates of the possible number of cells in future machines.

Like many other multimedia applications, image compression involves a significant amount of data processing for coding images. Sophisticated general-purpose processors with parallel architectures and advanced cache systems can be dedicated to enhancing performance for serial multimedia applications through parallelization. This thesis describes parallelization of the JasPer reference software for the JPEG-2000 image compression standard and presents results from simulation, and from hardware execution on a multicore processor where speedups of more than 2 are obtained with 4 processors. Results from execution and cache behavior analysis are presented to establish the expected speedup and to further characterize JasPer execution. The JasPer encoding process has been analyzed on a single processor for both simulated and hardware execution in order to obtain more insights into application behavior. On recent hardware platforms, the significant contributors to the total execution time have been identified through profiling. The granularity of parallelism for parallelizable loops have been analyzed for execution on real hardware. Cache behavior and memory access pattern have been studied closely for the simulated execution. To facilitate parallelization, selected parallelizable loops have been transformed in order to assist the partitioning of loop iterations for parallel execution and to increase workload granularity and reduce synchronization overhead. These modifications include loop index and body transformation, and loop fusion. A memory access pattern tracking feature has also been introduced for serial and parallel execution of a program in simulation. This feature tracks the number of memory accesses in a particular data region during a particular interval of time in order to gain additional insights into execution behavior. The multithreaded execution of the parallelized JasPer encoder presents a relatively balanced workload which indicates a reasonable efficiency for parallel execution. The generated images have been compared against their original images by using analytical tools to ensure the image quality and to verify correctness. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2011-10-29 00:10:43.437

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