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International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, California / Real-time high-volume telemetry data analysts have needs which require access to ever-increasing amounts of data, which must be processed in a seamless and coherent manner. BBN has developed a data analysis software architecture for use in distributed- and parallel-processing environments which is particularly well-suited for telemetry streams. BBN is currently using this software at two Navy sites to do realtime data analysis. The architecture provides data-source management, data-stream fusion, and data extraction all in a modular, scalable framework. Because of the scalable nature of the software, it can easily accommodate high data rates.

The methods of Scott-Strachey semantics are applied to the problem of writing programs for parallel computers, using serial languages such as are in common use, with compilers which attempt to discover and exploit potential parallelism in independent sections of program. A mathematical model of a parallel computer is first developed in detail, and in chapters 1 and 2 three basic conditions are derived which together ensure determinacy of operation in a parallel machine, first in purely semantic terms, then in a form more related to the syntactic structure of a language. The remaining chapters apply these basic conditions to three actual languages, showing how the conditions can be reduced to purely syntactic (hence compiler evaluable) tests. Chapter 3 uses a very simple language to introduce the techniques required. Chapter 4 adds procedures, with all the complexity they involve. Chapter 5 considers the rather more fruitful area of arrays and loops. The result, in all but the most trivial cases, is a rather complicated set of conditions which, while they produce the desired effect, suggest that today's commonly used languages are not the most suitable method of exploiting parallel computers.

Ho-Fung Leung. / Thesis (M.Ph.)--Chinese University of Hong Kong, 1988. / Bibliography: leaves [2-6], 3rd group.

by Wong Yiu Chung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1991. / Bibliography: leaves [100]-[101] / Acknowledgement / Abstract / Chapter 1. --- Introduction --- p.1-1 / Chapter 2. --- Alternately-Twisted Cube: Definition & Graph-Theoretic Properties --- p.2-1 / Chapter 2.1. --- Construction --- p.2-1 / Chapter 2.2. --- Topological Properties --- p.2-12 / Chapter 2.2.1. --- "Node Degree, Link Count & Diameter" --- p.2-12 / Chapter 2.2.2. --- Node Symmetry --- p.2-13 / Chapter 2.2.3. --- Sub cube Partitioning --- p.2-18 / Chapter 2.2.4. --- Distinct Paths --- p.2-23 / Chapter 2.2.5. --- Embedding other networks --- p.2-24 / Chapter 2.2.5.1. --- Rings --- p.2-25 / Chapter 2.2.5.2. --- Grids --- p.2-29 / Chapter 2.2.5.3. --- Binary Trees --- p.2-35 / Chapter 2.2.5.4. --- Hypercubes --- p.2-42 / Chapter 2.2.6. --- Summary of Comparison with the Hypercube --- p.2-44 / Chapter 3. --- Network Properties --- p.3-1 / Chapter 3.1. --- Routing Algorithms --- p.3-1 / Chapter 3.2. --- Message Transmission: Static Analysis --- p.3-5 / Chapter 3.3. --- Message Transmission: Dynamic Analysis --- p.3-13 / Chapter 3.4. --- Broadcasting --- p.3-17 / Chapter 4. --- Parallel Processing on the Alternately-Twisted Cube --- p.4-1 / Chapter 4.1. --- Ascend/Descend class algorithms --- p.4-1 / Chapter 4.2. --- Combining class algorithms --- p.4-7 / Chapter 4.3. --- Numerical algorithms --- p.4-8 / Chapter 5. --- "Summary, Comparison & Conclusion" --- p.5-1 / Chapter 5.1. --- Summary --- p.5-1 / Chapter 5.2. --- Comparison with other hypercube-like networks --- p.5-2 / Chapter 5.3. --- Conclusion --- p.5-7 / Chapter 5.4. --- Possible future research --- p.5-7 / Bibliography

by Ding Quan-Long. / Thesis (Ph.D.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references (p. 135-141). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web.

Qian Zhengfeng. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 127-129). / Abstracts in English and Chinese. / Chapter Chapter 1 --- Groundwork --- p.1 / Chapter 1.1 --- Introduction --- p.1 / Chapter 1.2 --- Exchange Patterns --- p.5 / Chapter 1.3 --- Multistage Networks --- p.9 / Chapter 1.3.1 --- Multistage Networks --- p.9 / Chapter 1.3.2 --- Banyan-type Networks --- p.11 / Chapter 1.4 --- Networks of Sorting Cells --- p.15 / Chapter 1.5 --- Symbolic Representation and Matrix Representation --- p.19 / Chapter 1.5.1 --- Symbolic Representation of a Multistage Interconnection Network --- p.19 / Chapter 1.5.2 --- Symbolic Representation of a Network of Sorting Cells --- p.21 / Chapter 1.5.3 --- Matrix Representation of a Network of Sorting Cells --- p.22 / Chapter 1.6 --- Summary --- p.24 / Chapter Chapter 2 --- Construction of Generalized Bitonic Sorters by Merging Rotated Monotonic Sequences --- p.25 / Chapter 2.1 --- Merging Networks --- p.25 / Chapter 2.1.1 --- Recursive 2-stage Construction --- p.26 / Chapter 2.1.2 --- UC/CU Non-blocking Switches --- p.35 / Chapter 2.1.3 --- Circular Sorters and Merging Networks --- p.41 / Chapter 2.2 --- Construction of Generalized Bitonic Sorters --- p.48 / Chapter 2.2.1 --- Bitonic Ar-sorters and Bitonic Dr-sorters --- p.48 / Chapter 2.2.2 --- Algorithms for Construction of Generalized Bitonic Sorters by Merging Rotated Monotonic Sequences --- p.51 / Chapter 2.3 --- Summary --- p.73 / Chapter Chapter 3 --- Construction of Generalized Bitonic Sorters by Cross-k Cell Rearrangement --- p.74 / Chapter 3.1 --- Cross-k Cell Rearrangement on a Multistage Network --- p.74 / Chapter 3.1.1 --- Intra-stage Cell Rearrangement --- p.74 / Chapter 3.1.2 --- Equivalence of Networks --- p.77 / Chapter 3.1.3 --- Cross-k Cell Rearrangement --- p.80 / Chapter 3.2 --- Construction of Generalized Bitonic Sorters --- p.85 / Chapter 3.3 --- Summary --- p.99 / Chapter Chapter 4 --- Redundancy of the Bitonic Network --- p.100 / Chapter 4.1 --- Counting of Identified Generalized Bitonic Sorters --- p.100 / Chapter 4.2 --- Redundancy of the Bitonic Network --- p.110 / Epilogue --- p.112 / Appendix C Program for Exhaustive Search of 8×8 Generalized Bitonic Sorters --- p.113 / References --- p.127

Thesis (B.A.)--Haverford College, Dept. of Computer Science, 2003. / Includes bibliographical references.

Modern superscalar processors exploit instruction-level parallelism (ILP) by issuing multiple instructions in a single cycle because of increasing demand for higher performance in computing. However, stalls due to cache misses severely degrade the performance by disturbing the exploitation of ILP. Multiprocessors also greatly exacerbate the memory latency problem. In SMPs, contention due to the shared bus located between the processors's L2 cache and the shared memory adds additional delay to the memory latency. In distributed shared memory (DSM) systems, the memory latency problem becomes even more severe because a miss on the local memory requires access to remote memory. This limits the performance because the processor can not spend its time on useful work until the reply from the remote memory is received. There are a number of techniques that effectively reduce the memory latency. Multithreadings has emerged as one of the most promising and exciting techniques to tolerate memory latency. This thesis aims to realize a simulator that supports software-controlled multithreadings environment on a Distributed Shared Memory and to show preliminary simulation results. / Graduation date: 2000