International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, California / Real-time high-volume telemetry data analysts have needs which require access to ever-increasing amounts of data, which must be processed in a seamless and coherent manner. BBN has developed a data analysis software architecture for use in distributed- and parallel-processing environments which is particularly well-suited for telemetry streams. BBN is currently using this software at two Navy sites to do realtime data analysis. The architecture provides data-source management, data-stream fusion, and data extraction all in a modular, scalable framework. Because of the scalable nature of the software, it can easily accommodate high data rates.

International Telemetering Conference Proceedings / October 25-28, 1993 / Riviera Hotel and Convention Center, Las Vegas, Nevada / This paper describes a real-time implementation of the pattern recognition technology originally developed by BBN [Delatizky et al] for post-processing of time-sampled telemetry data. This makes it possible to monitor a data stream for a characteristic shape, such as an arrhythmic heartbeat or a step-response whose overshoot is unacceptably large. Once programmed to recognize patterns of interest, it generates a symbolic description of a time-series signal in intuitive, object-oriented terms. The basic technique is to decompose the signal into a hierarchy of simpler components using rules of grammar, analogous to the process of decomposing a sentence into phrases and words. This paper describes the basic technique used for pattern recognition of time-series signals and the problems that must be solved to apply the techniques in real time. We present experimental results for an unoptimized prototype demonstrating that 4000 samples per second can be handled easily on conventional hardware.

ITC/USA 2014 Conference Proceedings / The Fiftieth Annual International Telemetering Conference and Technical Exhibition / October 20-23, 2014 / Town and Country Resort & Convention Center, San Diego, CA / Data acquisition for flight test is typically handled by dedicated hardware which performs specific functions and targets specific interfaces and buses. Through the use of an FPGA state machine based design approach, performance and robustness can be guaranteed. Up to now sufficient flexibility has been provided by allowing the user to configure the hardware depending on the particular application. However by allowing custom algorithms to be run on the data acquisition hardware, far greater control and flexibility can be offered to the flight test engineer. As the volume of the acquired data increases, this extra control can be used to vastly reduce the amount of data to be recorded or telemetered. Also real-time analysis of test points can now be done where post processing would previously have been required. This paper examines examples of data acquisition, recording and processing and investigates where data reduction and time savings can be achieved by enabling the flight test engineer to run his own algorithms on the hardware.

International Telemetering Conference Proceedings / October 13-16, 1986 / Riviera Hotel, Las Vegas, Nevada / The Boeing Commercial Airplane Company presently uses an Airborne Data Analysis and Monitor System (ADAMS) to support extensive qualification testing on new and modified commercial aircraft. The ADAMS system consists of subsystems controlled by independent processors which preprocess serial PCM data, perform application-specific processing, provide graphic display of data, and manage mass storage resources. Setup and control information is passed between processors using the Ethernet protocol on a fiber optic network. Tagged data is passed between processors using a data bus with networking characteristics. During qualification tests, data are dynamically selected, analyses performed, and results recorded. Decisions to proceed or repeat tests are made in real time on the aircraft. Instrumentation in present aircraft includes up to 3700 sensors, with projections for 5750 sensors in the next generation. Concurrently, data throughput rates are increasing, and data preprocessing requirements are becoming more complex. Fairchild Weston Systems, Inc., under contract to Boeing, has developed an Acquisition Interface Assembly (AIA) which accepts multiple streams of PCM data, controls recording and playback on analog tape, performs high speed data preprocessing, and distributes the data to the other ADAMS subsystems. The AIA processes one to three streams in any of the standard IRIG PCM formats using programmable bit, frame and subframe synchronizers. Data from ARINC buses with embedded measurement labels, bus ID’s, and time tags may also be processed by the AIA. Preprocessing is accomplished by two high-performance Distributed Processing Units (DPU) operating in either pipeline or parallel environments. The DPU’s perform concatenation functions, number system conversions, engineering unit conversions, and data tagging for distribution to the ADAMS system. Time information, from either a time code generator or tape playback, may be merged with data with a 0.1 msec resolution. Control and status functions are coordinated by an embedded processor, and are accessible to other ADAMS processors via both the Ethernet interface and a local operator’s terminal. Because the AIA assembly is used in aircraft, the entire functional capability has been packaged in a 14-inch high, rack-mountable chassis with EMI shielding. The unit has been designed for high temperature, high altitude, vibrating environments. The AIA will be a key element in aircraft qualification testing at Boeing well into the next generation of airframes, and specification, design, development, and implementation of the AIA has been carried out with the significance of that fact in mind.

<p>Server-based architectures have recently generated more interests and are currently considered for usage for communication in networks. In parallel, switched Ethernet technology has been widely adopted and used in lots of networked systems. Current requirements of networks for supporting real-time guarantees while being flexible at the same time have made the network designers to consider addition of some features to common switches. The FTT-Enabled Ethernet switch is a switch that has been developed to support the FTT (Flexible Time Triggered) paradigm. Recently, servers have been added in these types of switches in order to efficiently manage their allocated bandwidth to different types of messages.</p><p>A hierarchical network of Ethernet switches might be designed in different ways according to the overall goals and properties of the network. In this thesis, after a study on different design solutions, an architecture has been proposed based on FTT-enabled switches, motivated by their support of real-time constraints and server-based communication features. After having created the architecture, a protocol for bandwidth reservation for this hierarchically composed Ethernet switch architecture is developed. Behavior of the designed protocol is described in detail and it has been modeled using Uppaal. Moreover, the temporal behavior (timing) of the network is presented.</p>

The growing amount and diversity of functions to be implemented by the current and future embedded applications (like, for example, in automotive electronics) have shown that, in many cases, time-triggered and event-triggered functions have to coexist on the computing nodes and to interact over the communication infrastructure. When time-triggered and event-triggered activities have to share the same processing node, a natural way for the execution support can be provided through a hierarchical scheduler. Similarly, when such heterogeneous applications are mapped over a distributed architecture, the communication infrastructure should allow for message exchange in both time-triggered and event-triggered manner in order to ensure a straightforward interconnection of heterogeneous components. This thesis studies aspects related to the analysis and design optimisation for safety-critical hard real-time applications running on hierarchically scheduled distributed embedded systems. It first provides the basis for the timing analysis of the activities in such a system, by carefully taking into consideration all the interferences that appear at run-time between the processes executed according to different scheduling policies. Moreover, due to the distributed nature of the architecture, message delays are also taken into consideration during the timing analysis. Once the schedulability analysis has been provided, the entire system can be optimised by adjusting its configuration parameters. In our work, the entire optimisation process is directed by the results from the timing analysis, with the goal that in the end the timing constraints of the application are satisfied. The analysis and design methodology proposed in the first part of the thesis is applied next on the particular category of distributed systems that use FlexRay as a communication protocol. We start by providing a schedulability analysis for messages transmitted over a FlexRay bus, and then by proposing a bus access optimisation algorithm that aims at improving the timing properties of the entire system. For all the problems that we investigated, we have carried out extensive experiments in order to measure the efficiency of the proposed solutions. The results have confirmed both the importance of the addressed aspects during system-level design, and the applicability of our techniques for analysing and optimising the studied systems.

Server-based architectures have recently generated more interests and are currently considered for usage for communication in networks. In parallel, switched Ethernet technology has been widely adopted and used in lots of networked systems. Current requirements of networks for supporting real-time guarantees while being flexible at the same time have made the network designers to consider addition of some features to common switches. The FTT-Enabled Ethernet switch is a switch that has been developed to support the FTT (Flexible Time Triggered) paradigm. Recently, servers have been added in these types of switches in order to efficiently manage their allocated bandwidth to different types of messages. A hierarchical network of Ethernet switches might be designed in different ways according to the overall goals and properties of the network. In this thesis, after a study on different design solutions, an architecture has been proposed based on FTT-enabled switches, motivated by their support of real-time constraints and server-based communication features. After having created the architecture, a protocol for bandwidth reservation for this hierarchically composed Ethernet switch architecture is developed. Behavior of the designed protocol is described in detail and it has been modeled using Uppaal. Moreover, the temporal behavior (timing) of the network is presented.

Ubiquitous deployment of embedded systems is having a substantial impact on our society, since they interact with our lives in many critical real-time applications. Typically, embedded systems used in safety or mission critical applications (e.g., aerospace, avionics, automotive or nuclear domains) work in harsh environments where they are exposed to frequent transient faults such as power supply jitter, network noise and radiation. They are also susceptible to errors originating from design and production faults. Hence, they have the design objective to maintain the properties of timeliness and functional correctness even under error occurrences. Fault-tolerance plays a crucial role towards achieving dependability, and the fundamental requirement for the design of effective and efficient fault-tolerance mechanisms is a realistic and applicable model of potential faults and their manifestations. An important factor to be considered in this context is the random nature of faults and errors, which, if addressed in the timing analysis by assuming a rigid worst-case occurrence scenario, may lead to inaccurate results. It is also important that the power, weight, space and cost constraints of embedded systems are addressed by efficiently using the available resources for fault-tolerance. This thesis presents a framework for designing predictably dependable embedded real-time systems by jointly addressing the timeliness and the reliability properties. It proposes a spectrum of fault-tolerance strategies particularly targeting embedded real-time systems. Efficient resource usage is attained by considering the diverse criticality levels of the systems' building blocks. The fault-tolerance strategies are complemented with the proposed probabilistic schedulability analysis techniques, which are based on a comprehensive stochastic fault and error model.

No description available.

Yes / Reliability evaluation for ensuring the uninterrupted system operation is an integral part of dependable system development. Model-based safety analysis (MBSA) techniques such as Hierarchically Performed Hazard Origin and Propagation Studies (HiP-HOPS) have made the reliability analysis process less expensive in terms of effort and time required. HiP-HOPS uses an analytical modelling approach for Fault tree analysis to automate the reliability analysis process, where each system component is associated with its failure rate or failure probability. However, such non-state-space analysis models are not capable of modelling more complex failure behaviour of component like failure/repair dependencies, e.g., spares, shared repair, imperfect coverage, etc. State-space based paradigms like Markov chain can model complex failure behaviour, but their use can lead to state-space explosion, thus undermining the overall analysis capacity. Therefore, to maintain the benefits of MBSA while not compromising on modelling capability, in this paper, we propose a conceptual framework to incorporate complex basic events in HiP-HOPS. The idea is demonstrated via an illustrative example. / DEIS H2020 Project under Grant 732242.