Abstract In this thesis, a Multi-gate PD SOI Device is realized. The inverse narrow channel effect of the device is also studied. In the Multi-gate PD SOI structure, it has three-surface gate on the silicon MESA Island, which can promote the device performance. However, for eliminating the abnormal corner leakage current in the MESA Island, the process of rounded corner is used. In order to overcome the floating body effect, we use the Schottky body contact. According to the 3-D DAVINCI device simulation and the measurement results, the Multi-gate PD SOI device presents the excellent characteristics: low threshold voltage, low subthreshold factor and high breakdown voltage. In addition, comparing the Multi-gate device with that of the conventional one, the excess drain current gain is observed. In order to understand the behavior of INCE in Multi-gate PD SOI Device in depth, we use the concept of overlap depletion region to derive the expressions of threshold voltage shift. Owing to the device has rounded corner, we also study the rounded corner effect in the model formulation. Comparing calculation with that of the experiment one, the calculation shows agreement with the experiments.

abstract: There will always be a need for high current/voltage transistors. A transistor that has the ability to be both or either of these things is the silicon metal-silicon field effect transistor (MESFET). An additional perk that silicon MESFET transistors have is the ability to be integrated into the standard silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) process flow. This makes a silicon MESFET transistor a very valuable device for use in any standard CMOS circuit that may usually need a separate integrated circuit (IC) in order to switch power on or from a high current/voltage because it allows this function to be performed with a single chip thereby cutting costs. The ability for the MESFET to cost effectively satisfy the needs of this any many other high current/voltage device application markets is what drives the study of MESFET optimization. Silicon MESFETs that are integrated into standard SOI CMOS processes often receive dopings during fabrication that would not ideally be there in a process made exclusively for MESFETs. Since these remnants of SOI CMOS processing effect the operation of a MESFET device, their effect can be seen in the current-voltage characteristics of a measured MESFET device. Device simulations are done and compared to measured silicon MESFET data in order to deduce the cause and effect of many of these SOI CMOS remnants. MESFET devices can be made in both fully depleted (FD) and partially depleted (PD) SOI CMOS technologies. Device simulations are used to do a comparison of FD and PD MESFETs in order to show the advantages and disadvantages of MESFETs fabricated in different technologies. It is shown that PD MESFET have the highest current per area capability. Since the PD MESFET is shown to have the highest current capability, a layout optimization method to further increase the current per area capability of the PD silicon MESFET is presented, derived, and proven to a first order. / Dissertation/Thesis / M.S. Electrical Engineering 2011