As the mobile electronic products development are more and more popular such as mobile phone, digital camera, PDA¡Ketc. Each of company releases variable kind of mobile products, and every portable machine has plenty of functions. A low power consumption design is a significant issue which academics and engineers concern. It would be a major progress if the approach which can drop off the power consumption successfully. The mobile electronic products have more application programs than before and the size of LCD increases continuously, so that the power consumption becomes large. Therefore, expanding the life of battery would be a significant issue. Besides, the process technology has improved day by day, and it would influence the supply voltage be declined. It represents the power management would influence the power consumption of circuit directly. Comparing to drop down the entire IC power consumption and not to influence the performance of IC, the thesis employs the algorithm that searches the Critical Path and embeds the Level Converter Logic into digital circuit. It can offer the proper supply voltage to circuits which do not want to bigger supply voltage for reduce power consumption. However, the process variation (Inter-Die or Intra-Die) may transform the original Critical Path, the Critical Path which searches through the static timing analysis would not correct. To conquer this problem, the thesis provides the statistical approach to analysis timing. It would search Path Sensitivity which is exactly equal to the probability that a path is critical. Finally, the logic gate which is designed by us would replace the UMC 90nm standard cell through Cell-Based.