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The continuous growth in flight operations has led to public concern regarding the impact of aviation on the environment with its anthropogenic contribution to global warming. Several solutions have been proposed in order to reduce the environmental impact of aviation. However most of them are long term solutions such as new environmental friendly aircraft and engine designs. In this respect, management of aircraft trajectory and mission is a potential short term solution that can readily be implemented. Therefore, in order to truly understand the optimised environment friendly trajectories that can be actually deployed by airlines, it is important to investigate the impact of degraded engine performance on real aircraft trajectories at multi-disciplinary level. Several trajectory optimisation studies have been conducted in this direction in the recent past, but engines considered for the studies were clean and trajectories were ideal and simple. This research aims to provide a methodology to enhance the conventional approach of the aircraft trajectory optimisation problem by including engine degradation and real aircraft flight paths within the optimisation loop (framework); thereby the impact of engine degradation on optimum aircraft trajectories were assessed by quantifying the difference in fuel burn and emissions, when flying a trajectory which has been specifically optimised for an aircraft with degraded engines and flying a trajectory which has been optimised for clean engines. For the purpose of this study models of a clean and two levels of degraded engines have been developed that are similar to engines used in short range and long range aircraft currently in service. Degradation levels have been assumed based on the deterioration levels of Exhaust Gas Temperature (EGT) margin. Aircraft performance models have been developed for short range and long range aircraft with the capability of simulating (generating) vertical and horizontal flight profiles provides by the airlines. An emission prediction model was developed to assess NOx emissions of the mission. The contrail prediction model was adopted from previous studies to predict contrail formation. In addition, a multidisciplinary aircraft trajectory optimisation framework was developed and employed to analyse short range flight trajectories between London and Amsterdam and long range flight trajectories between London and Colombo under three cases. Case_1: Aircraft with clean engines, Case_2 and Case_3 were Aircraft with two different levels of degraded engines having a 5% and 10% Exhaust Gas Temperature (EGT) increase respectively. Three different multi objective optimisation studies were performed; (1) Fuel burn vs Flight time, (2) Fuel burn vs NOx emission, and (3) Fuel burn vs Contrails. Finally optimised trajectories generated with degraded engines were compared with the optimised trajectories generated with clean engines ... [cont].

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Proton Exchange Membrane Fuel Cell (PEMFC) is the most commonly used type of hydrogen fuel cell and a promising solution for vehicular and stationary power applications. This research starts with an extensive review of the PEMFC research, including experimental testing, and performance modeling, and performance degradation modeling using relatively accurate and easy-to-use mechanistic models. Next, a new PEMFC performance degradation model is introduced by amending the semi-empirical, mechanistic performance model to support the design and control of PEMFC systems and fuel cell electric vehicles (FCEVs). The new model takes into account critical factors impacting PEMFC performance. The performance degradation due to the oxidation of catalyst platinum (Pt) and loss of active surface area is captured by fitting the degradation model parameters using experimental data to capture the observed PEMFC performance fading. The new performance degradation model is then tested and further improved under the four typical load modes that a PEMFC system experiences in a vehicular application under regular driving cycles. The model is also fitted with PEMFC experimental degradation data under different load modes to improve modeling accuracy. The new model is applied and tested using simulations of a representative FCEV. The actual power load on an 80 kW PEMFC system in the modeled FCEV was obtained using the Advanced Vehicle Simulator (ADVISOR) under the US EPA Urban Dynamometer Driving Schedule (UDDS). With the ability to predict the operation life of the PEMFC, the appropriate sizes of the PEMFC system and the energy storage system (ESS) can be determined. Improved power control and energy management can be developed to extend the operation life of the PEMFC and lower the lifecycle cost of the FCEV. / Graduate

The lighting retrofit method is adopted as one of the solutions to reduce lighting energy consumption and improve lighting quality in existing buildings. Lighting controls and energy-efficient light sources are used to achieve the goals of the lighting retrofit. Nowadays, Light-Emitting Diodes (LEDs) are replacing traditional lighting technology owing to their high efficiency and longevity. One of the advantages of LEDs is the controllability function, which allows users to set the light level according to their preferences. This saves more energy and satisfies users’ lighting needs. However, over time, the performance of lighting retrofit projects deteriorates subject to failure of the retrofitted lights. Therefore, to maintain the performance of lighting retrofit projects, maintenance must be planned and performed. The impacts of the users’ lighting level requirements on LEDs’ life characteristics and lighting system performance are investigated by using lighting controls. Light and occupancy sensors adjust artificial light to the light level required by users and detect the presence of users in the zones, respectively. Light sensors measure the average illuminance in the zones. The measured illuminance is compared to the users’ set illuminance; if the measured illuminance is higher than the users’ set illuminance, lamps are dimmed to meet users’ lighting preference, when the measured illuminance is less than the users’ set illuminance, lamps in the zone are replaced by new ones. The dimming level in each zone at each sampling interval is used to estimate the operating junction temperature, thereafter the degradation rate and luminous flux are calculated. Light levels at workspace are modelled using the lumen method. This model helps to quantify energy savings and predict when lamps will fail to deliver the required light levels. In existing studies, users’ lighting level requirements are neglected when investigating the lifetime of the lighting system; however, users’ profile and driving schemes affect the operating conditions of a lighting system. From the simulation results, it is noted that lumen output degradation increases when the user’s set illuminance is above the illuminance required under normal operating conditions and decreases when the user’s set illuminance is below the illuminance required under normal operating conditions. Increased lumen output degradation shortens the lifetime of LEDs and reduces energy savings, while decreased lumen output degradation extends the lifetime and increases energy savings. Generally, lighting retrofit projects contain a large lighting population; investigating when each lamp will fail can be time-consuming and costly. In this research, a mathematical model is formulated to model LEDs’ failure by analysing the statistical properties of the lumen degradation rates. Based on the statistical properties of the degradation rates, the cumulative probability of failure distribution and the survival function are modelled. The formulated survival function is incorporated into the lighting maintenance optimization problem to balance energy savings and maintenance costs. A case study carried out shows that, in 10 years, the optimal lighting maintenance plan would save up to 59% of lighting energy consumption with acceptable maintenance costs. It is found that the proposed maintenance plan is more cost-effective than full maintenance. It is concluded that lumen degradation failure should be considered when investigating the performance of lighting retrofit projects, as this may not only affect energy savings but also reduce the level of illumination, which can cause visual discomfort. The initial investment costs of LEDs are still a barrier to the implementation of LED lighting systems in residential buildings. Energy-efficiency projects often face hurdles to access capital investments because decision-makers and funders do not have enough information about operational savings the project can provide and specific financial requirements applied to efficiency investment. In this research, an optimization model is formulated to give decision-makers and funders detailed information about the performance and operational savings that a LED lighting retrofit project can offer and its economic viability. The lumen degradation failure model developed is used to monitor and estimate the energy savings, and the optimal maintenance plan is scheduled to replace failed lamps. In the existing studies, the economic analysis of the lighting retrofit projects is assessed based on lighting population decay due to burnout failure while in this research economic analysis is assessed by considering the lumen degradation failure. The case study results show that the substitution of halogen light bulbs with LED light bulbs could save up to 291.4 GWh of energy consumption, and reduce 273:92 103 tons of CO2 emissions over 10-year period. The optimization model formulated is effective to help the decision-makers and funders to quantify the savings and assess the economic viability of the LED lighting retroïnˇA˛t project. This optimization model can help the decision-makers and funders to make an informed decision. / Thesis (PhD (Electrical Engineering))--University of Pretoria, 2020. / Electrical, Electronic and Computer Engineering / PhD (Electrical Engineering) / Unrestricted

<p>The number of speed-limiting paths in modern digital integrated circuits (ICs) is in the range of millions. Due to un-modelled electrical effects and process variations in advanced fabrication technologies, it is difficult for pre-silicon timing analysis tools to provide accurate delay estimates. Hence, programmable delay elements are commonly inserted in high-performance circuits in order to provide a tuning mechanism at the post-silicon phase. Due to the large number of such tuning elements, finding the appropriate configuration bits for each element mandates an automated approach.</p> <p>In this thesis we present three contributions to the field of digital IC design automation that leverage the presence of programmable delay tuning elements. These new automated approaches are geared toward three distinct objectives. The first one is to maximize the circuit performance using a scalable algorithmic framework. The second objective is to combat the lifetime performance degradation caused by circuit aging. The final objective is to improve the timing of the scan enable signal during the at-speed testing of digital ICs.</p> <p>As the programmable delay tuning elements will become prevalent in the future generations of digital ICs, the contributions from this thesis will help improve the design methodologies that are expected to evolve in order to address at runtime the timing problems introduced by the increased fabrication process variability.</p> / Doctor of Philosophy (PhD)

O trabalho propõe um circuito para caracterização estatística do fenômeno Bias Temperature Instability (BTI). O circuito tem como base uma matriz de transistores para caracterização eficiente em larga escala de BTI. O design proposto visa o estudo da variabilidade de BTI dependente do tempo em dispositivos altamente miniaturizados. Para tanto se necessita medir centenas de dispositivos, a fim de se obter uma amostra estatisticamente significante. Uma vez que variações nos tempos de estresse e medida dos dispositivos podem gerar erros no processo de caracterização, o circuito implementa em chip (on-chip) o controle dos tempos de estresse e de medida, para que ocorra uma caracterização estatística precisa. O circuito de controle implementado faz com que todos dispositivos testados tenham os mesmos tempos de estresse e os mesmos tempos de recuperação (relaxamento). Desta forma, o circuito proposto melhora significantemente tanto a área utilizada quanto o tempo de medida, quando comparado a alternativas anteriormente implementadas. O leiaute do circuito foi realizado no novo nó tecnológico de 28 nanômetros do IMEC. / This work proposes an array-based evaluation circuit for efficient and massively parallel characterization of Bias Temperature Instability (BTI). This design is highly efficient when studying the BTI time-dependent variability in deeply-scaled devices, where hundreds of devices should be electrically characterized in order to obtain a statistically significant sample size. The circuit controls stress and measurement times for accurate statistical characterization, making sure all the devices characterized have the same stress and recovery times. It significantly improves both area and measurement time. The circuit layout is laid out in the new 28nm node IMEC technology.

O trabalho propõe um circuito para caracterização estatística do fenômeno Bias Temperature Instability (BTI). O circuito tem como base uma matriz de transistores para caracterização eficiente em larga escala de BTI. O design proposto visa o estudo da variabilidade de BTI dependente do tempo em dispositivos altamente miniaturizados. Para tanto se necessita medir centenas de dispositivos, a fim de se obter uma amostra estatisticamente significante. Uma vez que variações nos tempos de estresse e medida dos dispositivos podem gerar erros no processo de caracterização, o circuito implementa em chip (on-chip) o controle dos tempos de estresse e de medida, para que ocorra uma caracterização estatística precisa. O circuito de controle implementado faz com que todos dispositivos testados tenham os mesmos tempos de estresse e os mesmos tempos de recuperação (relaxamento). Desta forma, o circuito proposto melhora significantemente tanto a área utilizada quanto o tempo de medida, quando comparado a alternativas anteriormente implementadas. O leiaute do circuito foi realizado no novo nó tecnológico de 28 nanômetros do IMEC. / This work proposes an array-based evaluation circuit for efficient and massively parallel characterization of Bias Temperature Instability (BTI). This design is highly efficient when studying the BTI time-dependent variability in deeply-scaled devices, where hundreds of devices should be electrically characterized in order to obtain a statistically significant sample size. The circuit controls stress and measurement times for accurate statistical characterization, making sure all the devices characterized have the same stress and recovery times. It significantly improves both area and measurement time. The circuit layout is laid out in the new 28nm node IMEC technology.

O trabalho propõe um circuito para caracterização estatística do fenômeno Bias Temperature Instability (BTI). O circuito tem como base uma matriz de transistores para caracterização eficiente em larga escala de BTI. O design proposto visa o estudo da variabilidade de BTI dependente do tempo em dispositivos altamente miniaturizados. Para tanto se necessita medir centenas de dispositivos, a fim de se obter uma amostra estatisticamente significante. Uma vez que variações nos tempos de estresse e medida dos dispositivos podem gerar erros no processo de caracterização, o circuito implementa em chip (on-chip) o controle dos tempos de estresse e de medida, para que ocorra uma caracterização estatística precisa. O circuito de controle implementado faz com que todos dispositivos testados tenham os mesmos tempos de estresse e os mesmos tempos de recuperação (relaxamento). Desta forma, o circuito proposto melhora significantemente tanto a área utilizada quanto o tempo de medida, quando comparado a alternativas anteriormente implementadas. O leiaute do circuito foi realizado no novo nó tecnológico de 28 nanômetros do IMEC. / This work proposes an array-based evaluation circuit for efficient and massively parallel characterization of Bias Temperature Instability (BTI). This design is highly efficient when studying the BTI time-dependent variability in deeply-scaled devices, where hundreds of devices should be electrically characterized in order to obtain a statistically significant sample size. The circuit controls stress and measurement times for accurate statistical characterization, making sure all the devices characterized have the same stress and recovery times. It significantly improves both area and measurement time. The circuit layout is laid out in the new 28nm node IMEC technology.

<p>  </p> <p>Environmental challenges, increasing energy costs and demand, and upcoming regulations (e.g., new equipment performance ratings, phase-down of HFCs) are a few of the main drivers behind the research on advanced HVAC&R equipment. The HVAC&R systems are one of the largest energy consumers in both commercial and residential buildings and their operation is essential to ensure thermal comfort as well as other industrial needs. Within this context, large chillers provide chilled water to condition commercial buildings and the new generation of smart chillers feature variable speed compressors that enable active capacity modulation. In turn, variable speed operation along with other factors can contribute to performance degradation. Understanding mechanisms of degradation and developing models that enable predicting the decrease in performance with respect to the rated values are still open topics in the literature. </p> <p>The overarching goal of this research is to investigate the performance degradation of a water-cooled variable-speed screw chiller under long term operation and to gain insights on the behavior of the chiller under accelerated life testing. In particular, this thesis covers the initial task of designing an experimental test setup that enables performance testing according to the AHRI 550/590 standard. Once the experimental setup was commissioned, a set of four standard-conform baseline tests was conducted to map the rated performance of the chiller at both full and part-load conditions. After completing the baseline tests, an accelerated life test cycle procedure was developed and implemented in order to conduct 24/7 automated testing on the chiller. To this end, two test modes were established to simulate a real-life use of the chiller and induce high level of thermo-mechanical stresses on the compressor. Furthermore, eight recurring baseline tests were conducted to determine the performance behavior after 1000 operating hours. Finally, a preliminary system model was set up. This thesis describes the design of the system, the commissioning and control and provides insights on the performance testing as well as long-term testing methodology and the modeling work that was done so far. </p>