The purpose of my thesis is to create one-person show lasting approximately twenty minutes. The following paper contains the step-by-step process of developing this piece of work, audience reactions to the final performance, and thoughts on continuing the process in hope of sharing the play with other communities. / text

The continued scaling of digital integrated circuits has led to an increasingly larger impact of process, supply voltage, and temperature (PVT) variations. The effect of these variations on logic cell and interconnect delays has introduced challenges to both circuit performance (timing)verification and optimization. In order for us to fully take advantage of the benefits of technology scaling, it is essential that ``variation-aware''techniques for performance verification and optimization be developed and used in modern design flows. In this thesis such techniques for both performance verification and optimization are presented. First, we present a fast method for finding the worst-case slacks over all process and environmental corners. This method uses the standard set of PVT corners available in industry, and provides large runtime gains while maintaining a high degree of accuracy. After that, we propose an efficient block-based parameterized timing analysis technique that can accurately capture circuit delays at every point in the parameter space, by reporting all paths that can become critical. This method employs parameterized static timing analysis (PSTA) variability models, and allows one to easily examine local robustness to parameters in different regions of the parameter space. Next, we introduce an optimization method that alters clock network lines so that a circuit meets its timing constraints at all PVT settings under PSTA variability models. This is formulated as a Linear Program (LP), which is based on a clock skew optimization formulation, and as a result it can be solved efficiently. Finally, we present a method that uses characterized, pre-silicon, PSTA variational timing models to identify speedpaths that can best explain the observed delay measurements during silicon debug. This is a crucial step, required for both ``fixing'' failing paths and for accurate learning from silicon data.

The continued scaling of digital integrated circuits has led to an increasingly larger impact of process, supply voltage, and temperature (PVT) variations. The effect of these variations on logic cell and interconnect delays has introduced challenges to both circuit performance (timing)verification and optimization. In order for us to fully take advantage of the benefits of technology scaling, it is essential that ``variation-aware''techniques for performance verification and optimization be developed and used in modern design flows. In this thesis such techniques for both performance verification and optimization are presented. First, we present a fast method for finding the worst-case slacks over all process and environmental corners. This method uses the standard set of PVT corners available in industry, and provides large runtime gains while maintaining a high degree of accuracy. After that, we propose an efficient block-based parameterized timing analysis technique that can accurately capture circuit delays at every point in the parameter space, by reporting all paths that can become critical. This method employs parameterized static timing analysis (PSTA) variability models, and allows one to easily examine local robustness to parameters in different regions of the parameter space. Next, we introduce an optimization method that alters clock network lines so that a circuit meets its timing constraints at all PVT settings under PSTA variability models. This is formulated as a Linear Program (LP), which is based on a clock skew optimization formulation, and as a result it can be solved efficiently. Finally, we present a method that uses characterized, pre-silicon, PSTA variational timing models to identify speedpaths that can best explain the observed delay measurements during silicon debug. This is a crucial step, required for both ``fixing'' failing paths and for accurate learning from silicon data.

The goal of this independent thesis is to follow through the process of learning Brahms concerto no. 1 from the very beginning until the performance. The goal is to provide an analysis of this process, thus understanding it better and also gaining new insights in what can be improved.  I used a diary of the practicing process to write down my experiences, videos from the practicing room and performance, analysis of the practicing methods, and also analysis of the performances as tools to investigate the topic. I hope that this thesis will be a work of interest for musicians who are interested in getting new insights into the practicing and performing process of a pianist.

The thesis deals with design of new processes of business department in IT company which provides server hosting, web hosting and domain registration services. These processes come from identification and analysis of current processes and the theory of business department management. Key Performance Indicators (KPIs) were set for selected processes which can be used for managing the company as a whole. Models of processes were created due to EPC notation. New processes were designed to continuously create data in CRM information system providing evidential and information support necessary for business department management, including the possibility of measuring its performance. Processes also automatize often repetitive activities and provide relevant information to other affected business units within the company. Contribution of the thesis lies in results of analysis of current identified processes containing solution proposals of discovered problems and newly created process models. Both can be used as a pattern for optimization of current processes in already existing organization or for designing new process models in new organization in the same or similar field of business.