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The use of resonant CMOS frequency dividers with direct injection in frequencysynthesizers has increased in recent years due to their lower power consumptioncompared to conventional digital prescalers. The theoretical and experimentalaspects of these dividers have received great attention. This masters thesis workis a continuation of earlier work, based on the fundamentals of Injection-LockedFrequency Dividers (ILFD’s). The LC CMOS ILFD with direct injection is wellknownfor its divide-by-2 capability. However, it does not divide well by oddnumbers. The goal of this master thesis work is to modify the LC CMOS ILFDwith direct injection so that it can divide equally well by odd and even integers.In this master thesis report, an introduction to the basic concepts behindInjection-Locked frequency dividers is first presented. Some of the previous workand the background of a reference LC CMOS ILFD design are studied. The author,studied the reference design, and the experimental setup used for characterizingit’s locking behavior. The algorithm used to characterize the locking behavior ofthis ILFD are explored to reproduce the results for divide-by-even numbers for theexisting ILFD topology. Using a Spice model these results are also reproduced insimulations.Over the years, numerous ILFD circuit topologies have been proposed, most ofwhich have been optimized for division by even numbers, especially divide-by-2.It has been more difficult to realize division by odd numbers, such as divide-by-3.This master thesis work develops a simple modification to an LC CMOS injectionlocked frequency divider (ILFD) with direct injection, which gives it a wide lockingrange both in the “divide-by-odd number” mode and in the conventional “divideby-even number” regime, thereby opening up applications which require frequencydivision by an odd number. The work presents the circuit architecture, SPICEsimulations and experimental validation.

Στόχος της διπλωματικής εργασίας είναι η σχεδίαση ενός συστήματος που να επιτρέπει την μελέτη των τεχνικών Σύνθεσης Συχνοτήτων με βρόχο κλειδωμένης φάσης μέσω του RMCLab. Στη παρούσα διπλωματική εργασία μελετήθηκε και σχεδιάστηκε το κατάλληλο υλικό (hardware) και λογισμικό (software) έτσι ώστε να δίνεται η δυνατότητα μελέτης του βρόχου σύνθεσης συχνότητας χωρίς κανένα ουσιαστικό περιορισμό. Ο χρήστης του συστήματος που κατασκευάστηκε σ’ αυτή τη διπλωματική εργασία μπορεί να μελετήσει βρόχους σύνθεσης συχνοτήτων που υλοποιούνται με όλες τις γνωστές μέχρι σήμερα τεχνικές (πχ: Integer N, Fractional, ΣΔ), ή ακόμη να εφαρμόσει δικές του τεχνικές ή νέες, πρόσφατες τεχνικές όπως αυτή του DIPA. Μπορεί επιπλέον να σχεδιάσει και να χρησιμοποιήσει τους δικούς του διαιρέτες συχνότητας, τον δικό του phase/frequency comparator και ακόμη να επιλέξει μέσα από μία ευρεία περιοχή στοιχείων (αντιστάσεις πυκνωτές) για την υλοποίηση του φίλτρου του συνθέτη. Εκτιμούμε ότι το αποτέλεσμα αυτής της διπλωματικής εργασίας θα συμβάλει σημαντικά στην κατανόηση του βρόχου κλειδωμένης φάσης και του συνθέτη συχνοτήτων από τους φοιτητές, και επιπλέον θα διευκολύνει σημαντικά την υλοποίηση και πειραματική επιβεβαίωση νέων διατάξεων βασισμένων σε βρόχο κλειδωμένης φάσης. / The aim of this dissertation is the development and implementation of the appropriate hardware and software for enabling the study of the PLL based frequency synthesis techniques using the facilities of the RMCLab (Remote Monitored and Controlled Lab.). The RMCLab user is now able to study deeply on the well known techniques of frequency synthesis as Integer N, Fractional or ΣΔ, since the developed system enables him to access and customize any of the synthesizer components (dividers, phase/frequency detector, filter). Additionally, the system allows the user to apply new appeared frequency synthesis techniques such as the DIPA technique, or even to develop and experiment on his own ideas regarding frequency synthesis. It is anticipated that the system developed under this dissertation will enable students to deeply understand on the theory of phase locked loop and practice on various frequency synthesis techniques.

Στην παρούσα Διπλωματική Εργασία μελετάται η αρχιτεκτονική και τα χαρακτηριστικά ενός νέου συνθέτη συχνοτήτων (Frequency Synthesizer) που βασίζεται στην τεχνική του βρόχου κλειδωμένης φάσης (Phase-Locked Loop). Η νέα αρχιτεκτονική ξεπερνά την δυσκολία του απλού συνθέτη συχνοτήτων να έχει ταυτόχρονα μικρό βήμα συχνότητας και μικρό χρόνο κλειδώματος, ενώ ταυτόχρονα διατηρεί και επαυξάνει την δυνατότητα των απλών συνθετών να απορρίπτουν τον θόρυβο φάσης, δίνοντας έτσι πολύ καλή ποιότητα σήματος εξόδου. Τα χαρακτηριστικά αυτά καθιστούν τον νέο συνθέτη πολύ ανταγωνιστικό. / This Diploma Thesis studies the architecture and the characteristics of a new Frequency Synthesizer which based on the Phase-Locked Loop technique. This new architecture overcomes the difficulty of the simple frequency synthesizer to have simultaneously small frequency step and small locking time, while maintains and enhances the possibility to reject phase noise. This concludes to the high quality of the output signal. The above characteristics make the new synthesizer very competitive.

This thesis investigates issues affecting grid synchronisation of VSC-HVDC systems with particular regard to, but not limited to, offshore wind power generation during the complex but potentially serious behaviours following solar storms. An averaged value model (AVM) for the contemporary modular multilevel converter (MMC) based VSC-HVDC system is developed and is used in combination with different phase-locked loop (PLL) models and the unified magnetic equivalent circuit (UMEC) transformer model to assess the impacts of geomagnetically induced current (GIC) on grid synchronisation of an offshore VSC-HVDC system. GIC is DC current flowing in the earth caused by strong geomagnetic disturbance events. GIC enters the electric utility grid via the grounded transformer neutral and can cause severe saturation to transformers. This in turn causes disruptions to grid synchronisation. The main contribution of this thesis is that effects of GIC are studied using the UMEC transformer model, which can model saturation. The assessment leads to the development of enhanced fundamental positive sequence control (EFPSC) which is capable of reducing the stress on the system during GIC events. The methods developed can also be applied to other non-symmetrical AC events occurring in VSC-HVDC such as single-phase faults. Additional contributions of the thesis are:A mathematical model of the MMC is derived and forms the foundation of the AVM. The AVM is verified against a detailed equivalent-circuit-based model and shows good accuracy. The PLL is the essential component for grid synchronisation of VSC-HVDC system. Different PLLs are studied in detail. Their performance is compared both qualitatively and quantitatively. This appears to have been done for the first time systematically in the public literature. The UMEC model is verified using hand calculation. Its saturation characteristic is matched to a predefined B-H curve and is also verified. The verifications show that this model is capable of modelling transformer saturation and thus is suitable for this study. The consolidation of the AVM, PLL, UMEC, GIC and EFPSC provides an insight into the how the MMC based VSC-HVDC system behaves under severe geomagnetic disturbances and the possible methods to mitigate the risks and impacts to the power grid.

京都大学 / 0048 / 新制・課程博士 / 博士(情報学) / 甲第18413号 / 情博第528号 / 新制||情||93(附属図書館) / 31271 / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 小野寺 秀俊, 教授 守倉 正博, 教授 佐藤 高史 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

No description available.

Phase Locked Loop (PLL) is an integral component of clock generation circuits. A third order Charge Pump PLL (CPPLL) is most widely employed PLL architecture due to its zero steady state phase error. A monolithic implementation of such a CPPLL presents numerous challenges to PLL designers, the number of such challenges vary depending on the process technology employed and the end application. One such challenge that is worth mentioning is the on-chip integration of the second order passive loop filter. The area occupied by the second order passive loop filter is mainly determined by the zero determining capacitance (CZ). A low loop bandwidth CPPLL has a higher CZ value, and hence consumes a larger die area than a large loop bandwidth CPPLL. Literature survey shows that the problem of higher CZ value in low loop bandwidth CPPLL is addressed by using some form of emulation techniques. A relatively simpler emulation technique is the use of dual charge pump based loop filter. Existing dual charge pump based loop filter consume extra elements (such as summer that need opamps to realize the summer function) for achieving low CZ value. These extra elements consume extra area and additional power. We present two types of Summer-Less Dual Charge Pump (SDCP) based loop filter designs that do not need extra elements and still achieves low CZ value and this is achieved by using a second charge pump in an appropriate way. A test chip was implemented in 0.13µm UMC MMRFCMOS process to verify the presented circuits. The presented SDCP based loop filter circuits are particularly useful in designs employing multiple CPPLL’s and design employing low loop bandwidth CPPLL’s. Another challenge worth-mentioning is the frequency ranges over which the PLL can be locked. The Voltage Controlled Oscillator (VCO) of PLL mainly determines the frequency locking range of a PLL. A typical VCO has a frequency locking range of usually 1:2 to 1:3. The VCO frequency tuning range reduces with reduction in supply voltage. This poses a serious problem in low supply voltage applications that demand a wide frequency locking range, sometimes greater than 1:3. We have addressed this problem of wide PLL lock range, by using an Analog Frequency Detector. A wide frequency lock range is achieved, either by dynamically modifying the VCO or the feedback divider of PLL. Both the approaches are equally feasible. The frequency detector is used for dynamically modifying the VCO or the feedback divider of PLL. Two test chips were implemented to verify the presented Analog Frequency Detector scheme. A testchip implemented in 0.25µm CSM analog process achieves wide frequency lock range by dynamically modifying the feedback divider of PLL. Another testchip implemented in 0.13µm UMC MMRFCMOS process achieves wide frequency lock range by dynamically modifying the center frequency of the VCO. Presented analog frequency detection scheme is particularly useful in applications that demand wide PLL lock range from a single die.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / O objetivo deste trabalho é contribuir com o desenvolvimento de uma técnica baseada em sistemas inteligentes que possibilite a localização exata ou aproximada do ponto de origem de uma Variação de Tensão de Curta Duração (VTCD) (gerada por uma falta) em um sistema de distribuição de energia elétrica. Este trabalho utiliza um Phase-Locked Loop (PLL) com o intuito de detectar as faltas. Uma vez que a falta é detectada, os sinais de tensão obtidos durante a falta são decompostos em componentes simétricas instantâneas por meio do método proposto. Em seguida, as energias das componentes simétricas são calculadas e utilizadas para estimar a localização da falta. Nesta pesquisa, são avaliadas duas estruturas baseadas em Redes Neurais Artificiais (RNAs). A primeira é projetada para classificar a localização da falta em um dos pontos possíveis e a segunda é projetada para estimar a distância da falta ao alimentador. A técnica aqui proposta aplica-se a alimentadores trifásicos com cargas equilibradas. No desenvolvimento da mesma, considera-se que há disponibilidade de medições de tensões no nó inicial do alimentador e também em pontos esparsos ao longo da rede de distribuição. O banco de dados empregado foi obtido através de simulações de um modelo de alimentador radial usando o programa PSCAD/EMTDC. Testes de sensibilidade empregando validação-cruzada são realizados em ambas as arquiteturas de redes neurais com o intuito de verificar a confiabilidade dos resultados obtidos. Adicionalmente foram realizados testes com faltas não inicialmente contidas no banco de dados a fim de se verificar a capacidade de generalização das redes. Os desempenhos de ambas as arquiteturas de redes neurais foram satisfatórios e demonstram a viabilidade das técnicas propostas para realizar a localização de faltas em redes de distribuição. / The aim of this work is to contribute to the development of a technique based on intelligent systems that allows the accurate location of the Short Duration Voltage Variations (SDVV) origin in an electrical power distribution system. Once the fault is detected via a Phase-Locked Loop (PLL), voltage signals acquired during the fault are decomposed into instantaneous symmetrical components by the proposed method. Then, the energies of the symmetrical components are calculated and used to estimate the fault location. In this work, two systems based on Artificial Neural Networks (ANN) are evaluated. The first one is designed to classify the fault location into one of predefined possible points and the second is designed to estimate the fault distance from the feeder. The technique herein proposed is applies to three-phase feeders with balanced loads. In addition, it is considered that there is availability of voltage measurements in the initial node of the feeder and also in sparse points along the distribution power grid. The employed database was made using simulations of a model of radial feeder using the PSCAD / EMTDC program. Sensitivity tests employing cross-validation are performed for both approaches in order to verify the reliability of the results. Furthermore, in order to check the generalization capability, tests with faults not originally contained in the database were performed. The performances of both architectures of neural networks were satisfactory and they demonstrate the feasibility of the proposed techniques to perform fault location on distribution grids.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / O objetivo deste trabalho é contribuir com o desenvolvimento de uma técnica baseada em sistemas inteligentes que possibilite a localização exata ou aproximada do ponto de origem de uma Variação de Tensão de Curta Duração (VTCD) (gerada por uma falta) em um sistema de distribuição de energia elétrica. Este trabalho utiliza um Phase-Locked Loop (PLL) com o intuito de detectar as faltas. Uma vez que a falta é detectada, os sinais de tensão obtidos durante a falta são decompostos em componentes simétricas instantâneas por meio do método proposto. Em seguida, as energias das componentes simétricas são calculadas e utilizadas para estimar a localização da falta. Nesta pesquisa, são avaliadas duas estruturas baseadas em Redes Neurais Artificiais (RNAs). A primeira é projetada para classificar a localização da falta em um dos pontos possíveis e a segunda é projetada para estimar a distância da falta ao alimentador. A técnica aqui proposta aplica-se a alimentadores trifásicos com cargas equilibradas. No desenvolvimento da mesma, considera-se que há disponibilidade de medições de tensões no nó inicial do alimentador e também em pontos esparsos ao longo da rede de distribuição. O banco de dados empregado foi obtido através de simulações de um modelo de alimentador radial usando o programa PSCAD/EMTDC. Testes de sensibilidade empregando validação-cruzada são realizados em ambas as arquiteturas de redes neurais com o intuito de verificar a confiabilidade dos resultados obtidos. Adicionalmente foram realizados testes com faltas não inicialmente contidas no banco de dados a fim de se verificar a capacidade de generalização das redes. Os desempenhos de ambas as arquiteturas de redes neurais foram satisfatórios e demonstram a viabilidade das técnicas propostas para realizar a localização de faltas em redes de distribuição. / The aim of this work is to contribute to the development of a technique based on intelligent systems that allows the accurate location of the Short Duration Voltage Variations (SDVV) origin in an electrical power distribution system. Once the fault is detected via a Phase-Locked Loop (PLL), voltage signals acquired during the fault are decomposed into instantaneous symmetrical components by the proposed method. Then, the energies of the symmetrical components are calculated and used to estimate the fault location. In this work, two systems based on Artificial Neural Networks (ANN) are evaluated. The first one is designed to classify the fault location into one of predefined possible points and the second is designed to estimate the fault distance from the feeder. The technique herein proposed is applies to three-phase feeders with balanced loads. In addition, it is considered that there is availability of voltage measurements in the initial node of the feeder and also in sparse points along the distribution power grid. The employed database was made using simulations of a model of radial feeder using the PSCAD / EMTDC program. Sensitivity tests employing cross-validation are performed for both approaches in order to verify the reliability of the results. Furthermore, in order to check the generalization capability, tests with faults not originally contained in the database were performed. The performances of both architectures of neural networks were satisfactory and they demonstrate the feasibility of the proposed techniques to perform fault location on distribution grids.