In this thesis, we firstly present a low-cost plasma display panel (PDP) data dispatcher for image enhancement. By taking advantage of the proposed ADS method with 10 subfields and data reordering, our design can reduce 20% of the PDP dispatcher cost and resolve the ¡§dynamic false contour¡¨ problem. Secondly, a bipolar-valued inner product processor for associative memory neural networks is proposed to compute the inner product of two bipolar-valued vectors. Our analysis shows that the delay of inner product is reduced significantly from O(2n) to O(n). We also propose a 3-dimensional address decoding structure associated with a corresponding data cell encoding arrangement for P+implant ROMs such that the data words are encoded and stored in the ROMs in a natural pattern. Not only is the size of the entire decoder shrunk, the access time and power dissipation is also greatly reduced, which is very suitable to be utilized in implantable devices. Finally, we introduce a multi-parameter implantable neural interface micro-stimulator system, including the external control module, the protocol, and the SOC (system-on-chip) chip. The proposed system is expected to carry out the externally given commands to stimulate the corresponding neural trunks. On the other way around, it can sense and deliver the response of the neural trunks to an external monitoring device in the future.

This thesis includes two topics. The first topic is a data dispatcher design of a digital image processor for plasma display panels, which can be used in a 42-inch plasma display panel (PDP). The second one is a low-power small-area digital I/O cell design. The data dispatcher is applied to a 42-inch panel, which is produced by AUO corporation, as a test platform. It comprises FPGAs and RAMs to carry out data dispatching. The solution is verified to provide a better image quality, while the cost is also reduced. Regarding the low-power small-area digital I/O cell, we propose a totally different concept in contrast to traditional I/O cells. It is focused on low power consumption and small area. The proposed design is carried out by TSMC 1P5M 0.25 mm CMOS process at 2.5 V power supply. The power consumption is measured to be at least 51.4% less than prior works. The area is proven to be at least 44% more efficient.