In this thesis, we will investigate the degradation of the low temperature polycrystalline silicon TFTs (LTPS TFTS) under the electrical stress. The electrical stress is divided into two parts of ac stress and dc stress. We used ac stress and dc stress conditions to stress different TFTs respectively and investigate the influence of grain boundary in n-type TFT and p-type TFT by use of electrical analysis. On the other hand, degradation mechanism was confirmed by measured capacitance. In n-type TFT, the SLS poly-Si TFT which contains GB perpendicular to the channel direction owns the higher ability against dc stress and poorer ability against ac stress than the poly-Si TFT which does not contain GB. The physical mechanism for these results has been reasonably deduced by use of TFT device simulation tool (ISE_TCAD). In p-type TFT, the enhancement phenomenon is always observed after dc or ac stress. There are both existed a power-law between the variation of the drain current with stress time. The slope of power-law is related to the shortening speed of effective channel length. In either dc stress or ac stress, there are two effective factors. The one factors of them is the degradation of poly-Si film, and another one is the effective channel length shortening. In the competition of these two effective factors, the GB-TFT has more obvious enhancement than GB-TFT during dc stress. Nevertheless, during the ac stress the GB-TFT is without larger enhancement than NGB-TFT because of serious poly-Si film damage.

In this thesis, we present a new Poly - Si TFT process method to overcome Self - heating effect and Floating body effect. The main drawback of a conventional Poly - Si TFT is the existence of self - heating effect and floating body effect. The self - heating effect leads to drain current reduced and the floating body effect leads to premature device breakdown and kink effects. Here, we utilize all kinds of different isolation technologies to form non - continuing buried layer. Between the non - continuing buried layer there are pass ways, which contact the active region and the substrate directly. Because of conventional LOCOS isolation technology has longer bird¡¦s beak, the familiar method of SILO and PBL isolation technologies are used to reduce bird¡¦s beak. Also, we use STI isolation technology to build up non - continuing buried layer, which can control the width of pass way more easily. It is proved from the measurement that the pass way can slow down the self - heating effect and the floating body effect successfully.

In this research, the degradation effect of the low temperature polycrystalline silicon TFTs (LTPS TFTs) under dynamic stress was investigated. The experiment results revealed that the degenerate behaviors of n- and p-type poly-Si were different. In p-channel TFT, it was observed that the degradation of threshold-voltage (Vth) was closely associated with the stress frequency of ac stress. The degradation was more serious at low-frequency stress than that at high-frequency stress. The degradation of electrical characteristics of device is mainly dominated by the self-heating enhanced negative bias temperature instability effect. Moreover, the increased temperature around the environment could make the degradation of characteristics more serious, such as Vth shift (fixed charge), degraded S.S (dangling bonds). We suggest that the generation of deep states originated from bond broken at both of grain-boundary and interface state was explained the degradation mechanism of threshold-voltage. In n-channel TFT, the degradation characteristics may be attributed to both of the temperature effect and the hot carrier effect under the different stress frequency. At low-frequency stress, Vth shift (positively) and mobility are increased after 100 seconds stress because of the temperature effect. However, Vth shift (negatively) and mobility are decreased after 500 seconds stress because of the effect of the state creation near the drain regime. At high-frequency stress, the times of the switch is numerous, and result in the on-state current decreased because of the trap state generated.