The integration of high voltage power transistors with control circuitry to form smart Power Integrated Circuits (PIC) has numerous applications in the areas of industrial and consumer electronics. These smart PICs must rely on the availability of high performance power transistors. In this thesis, a vertical U-shaped gate MOSFET (UMOS) and a lateral Extended Drain MOSFET (EDMOS) with enhanced electrical characteristics are proposed, developed and verified via experimental fabrication. The proposed new process and structure offers superior performance, such as low on-resistance, low gate charge and optimized high breakdown voltage. In the vertical power UMOS, a novel trenched Local Oxidation of Silicon (LOCOS) process has been applied to the vertical gate structure to reduce the gate-to-source overlap capacitance (Cgs). A 40% reduction in Cgs is achieved when compared to conventional UMOS. A specific on-resistance Ron, sp = 60m2·mm2 is observed, which is 45% better than that of the conventional UMOS. The improvement in the device’s Figure-of-Merit (FOM = Ron × Qg) is about 58%. A floating RESURF EDMOS (BV=55V, Ron,sp=36.5m2·mm2) with a 400% improvement in the Safe Operating Area (SOA) when compared to the conventional EDMOS structure is also presented. The proposed EDMOS employs both drain and iii source engineering to enhance SOA, not only via reducing the base resistance of the parasitic bipolar transistor, but also suppressing the base current of the parasitic bipolar transistor under high Vgs and high Vds conditions. A buried deep Nwell allows the device to have better trade-off between breakdown voltage and on-resistance. Finally, in order to achieve low gate charge in the EDMOS, a novel orthogonal gate electrode is proposed to reduce the gate-to-drain overlap capacitance (Cgd). The orthogonal gate has both horizontal and vertical sections for gate control. This device is implemented in a 0.18?m 30V HV-CMOS process. Compared to a conventional EDMOS with the same voltage and size, a 75% Cgd reduction is observed. The FOM is improved by 53%.

The integration of high voltage power transistors with control circuitry to form smart Power Integrated Circuits (PIC) has numerous applications in the areas of industrial and consumer electronics. These smart PICs must rely on the availability of high performance power transistors. In this thesis, a vertical U-shaped gate MOSFET (UMOS) and a lateral Extended Drain MOSFET (EDMOS) with enhanced electrical characteristics are proposed, developed and verified via experimental fabrication. The proposed new process and structure offers superior performance, such as low on-resistance, low gate charge and optimized high breakdown voltage. In the vertical power UMOS, a novel trenched Local Oxidation of Silicon (LOCOS) process has been applied to the vertical gate structure to reduce the gate-to-source overlap capacitance (Cgs). A 40% reduction in Cgs is achieved when compared to conventional UMOS. A specific on-resistance Ron, sp = 60m2·mm2 is observed, which is 45% better than that of the conventional UMOS. The improvement in the device’s Figure-of-Merit (FOM = Ron × Qg) is about 58%. A floating RESURF EDMOS (BV=55V, Ron,sp=36.5m2·mm2) with a 400% improvement in the Safe Operating Area (SOA) when compared to the conventional EDMOS structure is also presented. The proposed EDMOS employs both drain and iii source engineering to enhance SOA, not only via reducing the base resistance of the parasitic bipolar transistor, but also suppressing the base current of the parasitic bipolar transistor under high Vgs and high Vds conditions. A buried deep Nwell allows the device to have better trade-off between breakdown voltage and on-resistance. Finally, in order to achieve low gate charge in the EDMOS, a novel orthogonal gate electrode is proposed to reduce the gate-to-drain overlap capacitance (Cgd). The orthogonal gate has both horizontal and vertical sections for gate control. This device is implemented in a 0.18?m 30V HV-CMOS process. Compared to a conventional EDMOS with the same voltage and size, a 75% Cgd reduction is observed. The FOM is improved by 53%.

In this thesis, next generation low-voltage integrated power semiconductor devices are proposed and analyzed in terms of device structure and layout optimization techniques. Both approaches strive to minimize the power consumption of the output stage in DC-DC converters. In the first part of this thesis, we present a low-voltage CMOS power transistor layout technique, implemented in a 0.25µm, 5 metal layer standard CMOS process. The hybrid waffle (HW) layout was designed to provide an effective trade-off between the width of diagonal source/drain metal and the active device area, allowing more effective optimization between switching and conduction losses. In comparison with conventional layout schemes, the HW layout exhibited a 30% reduction in overall on-resistance with 3.6 times smaller total gate charge for CMOS devices with a current rating of 1A. Integrated DC-DC buck converters using HW output stages were found to have higher efficiencies at switching frequencies beyond multi-MHz. In the second part of the thesis, we present a CMOS-compatible lateral superjunction FINFET (SJ-FINFET) on a SOI platform. One drawback associated with low-voltage SJ devices is that the on-resistance is not only strongly dependent on the drift doping concentration but also on the channel resistance as well. To resolve the issue, a SJ-FINFET structure consisting of a 3D trench gate and SJ drift region was developed to minimize both channel and drift resistances. Several prototype devices were fabricated in a 0.5µm CMOS compatible process with nine masking layers. In comparison with conventional SJ-LDMOSFETs, the fabricated SJ-FINFETs demonstrated approximately 30% improvement in Ron,sp. This is a positive indication that the SJ-FINFET can become a competitive power device for sub-100V rating applications.

In this thesis, next generation low-voltage integrated power semiconductor devices are proposed and analyzed in terms of device structure and layout optimization techniques. Both approaches strive to minimize the power consumption of the output stage in DC-DC converters. In the first part of this thesis, we present a low-voltage CMOS power transistor layout technique, implemented in a 0.25µm, 5 metal layer standard CMOS process. The hybrid waffle (HW) layout was designed to provide an effective trade-off between the width of diagonal source/drain metal and the active device area, allowing more effective optimization between switching and conduction losses. In comparison with conventional layout schemes, the HW layout exhibited a 30% reduction in overall on-resistance with 3.6 times smaller total gate charge for CMOS devices with a current rating of 1A. Integrated DC-DC buck converters using HW output stages were found to have higher efficiencies at switching frequencies beyond multi-MHz. In the second part of the thesis, we present a CMOS-compatible lateral superjunction FINFET (SJ-FINFET) on a SOI platform. One drawback associated with low-voltage SJ devices is that the on-resistance is not only strongly dependent on the drift doping concentration but also on the channel resistance as well. To resolve the issue, a SJ-FINFET structure consisting of a 3D trench gate and SJ drift region was developed to minimize both channel and drift resistances. Several prototype devices were fabricated in a 0.5µm CMOS compatible process with nine masking layers. In comparison with conventional SJ-LDMOSFETs, the fabricated SJ-FINFETs demonstrated approximately 30% improvement in Ron,sp. This is a positive indication that the SJ-FINFET can become a competitive power device for sub-100V rating applications.

Power module design is needed for high system performance and reliability, especially in terms of high efficiency and high power density. Low parasitic impedance and thermal management is desired for the lower power loss and device stress. For power module with high efficiency and improved breakdown voltage, this thesis proposes a novel series-connected power MOSFETs module. Three IRF7832 MOSFETs (30 V breakdown voltage) in series are simulated in a chopper circuit. The drain-source voltage sharing in switching off-mode shows that the devices can share voltage within their breakdown ranges. The switching characteristics are studied, and the switching energy losses without parasitic inductance and with 5 nH parasitic inductances are 203.38 µJ and 316.49 µJ, respectively. The critical parasitic inductance is the one connecting the source of the upper MOSFET and the drain of the middle MOSFET. The switching energy loss due to critical parasitic inductance is about 44.4% of the total switching energy loss. The layout is designed for the double-substrates direct-bond module and wire-bonded module using direct-bond-copper (DBC) substrate. Based on layout dimensions and packaging materials, the packaging module's parasitic parameters are obtained using Ansoft® Q3D extractor. Using parasitic inductance values from simulation, the switching energy losses of direct-bond module and wire-bonded module are 296.18 µJ and 238.99 µJ, respectively. Thermal management is then studied using Ansoft® ePhysics. The MOSFET junction-to-air thermal resistances of the double-substrate direct-bond module and the single-substrate wire-bonded module are 33oC/W and 82oC/W, respectively. Hence, by comparing the direct-bond module with a wire-bonded power module, direct-bond module shows lower parasitic impedances and better thermal management. To test the breakdown voltage of series-connected power MOSFETs module, three TI DualCoolTM N-channel NexFET Power MOSFETs (25 V breakdown voltage) in series are assembled using flip-chip direct-bond technology. Three samples are assembled and the breakdown voltages are measured by using high-power curve tracer as 76 V, 82 V, and 72 V. The more accurate method for testing breakdown voltages by digital voltmeter obtains 77.51 V, 82.31 V, and 73.06 V. The series-connected power MOSFETs module shows compact volume, low parasitic impedances, thermal resistances and improved breakdown voltage. This power module has strong potential for use in applications that require minimized packaging size and parasitic inductance for high voltage, high switching frequency, and high efficiency. / Master of Science

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This thesis focuses on the design of high voltage MOSFET on SiC and its application in power electronic systems. Parameters extraction for 4H SiC MOS devices is the main focus of the first topic developed in this thesis. Calibration of two-dimensional (2-D) device and circuit simulators (MEDICI and SPICE) with state-of-the-art 4H SiC MOSFETs data are performed, which includes the mobility parameter extraction. The experimental data were obtained from lateral N-channel 4H SiC MOSFETs with nitrided oxide-semiconductor interfaces, exhibiting normal mobility behavior. The presence of increasing interface-trap density (Dit) toward the edge of the conduction band is included during the 2-D device simulation. Using measured distribution of interface-trap density for simulation of the transfer characteristics leads to good agreement with the experimental transfer characteristic. The results demonstrate that both MEDICI and SPICE simulators can be used for design and optimization of 4H SiC MOSFETs and the circuits utilizing these MOSFETs. Based on critical review of SiC power MOSFETs, a new structure of SiC accumulation-mode MOSFET (ACCUFET) designed to address most of the open issues related to MOS interface is proposed. Detailed analysis of the important design parameters of the novel structure is performed using MEDICI with the parameter set used in the calibration process. The novel structure was also compared to alternative ACCUFET approaches, specifically planar and trench-gate ACCUFETs. The comparison shows that the novel structure provides the highest figure of merit for power devices. The analysis of circuit advantages enabled by the novel SiC ACCUFET is given in the final part of this thesis. The results from circuit simulation show that by utilizing the novel SiC ACCUFET the operating frequency of the circuit can be increased 10 times for the same power efficiency of the system. This leads to dramatic improvements in size, weight, cost and thermal management of power electronic systems.

No description available.

Synchronous buck converter based multiphase architectures are evaluated to determine whether or not the most widespread voltage regulator topology can meet the power delivery requirements of next generation computer microprocessors. According to the prognostications, the load current will rise to 200A along with the decrease of the supply voltage to 0.5V and staggering tight dynamic and static load line tolerances. In view of these demands, researchers face serious challenges to bring forth compliant solutions that can further offer acceptable conversion efficiencies and minimum mainboard area occupancy. Among the most prominent investigation fronts are those surveying fundamental technology improvements aiming at making power semiconductor devices more effective at high switching frequency. The latter is of critical importance as the increase of the switching frequency is fundamentally recognized as the way forward to enhance power density conversion. Provided that switching losses must be kept low to enable the miniaturization of the filter components, one primary goal is to cope with semiconductor and system integration technologies enabling fast dynamic operation of ultra-low ON resistance power switches. This justifies the main focus of this thesis work, centered around a comprehensive analysis of the MOSFET switching behavior in the synchronous buck converter. The MOSFETs dynamic operation, far from being well describable with the traditional clamped inductive hard-switching mode, is strongly influenced by a number of frequently ignored linear and nonlinear parasitic elements that must be taken into account in order to fully predict real switching waveforms, understand their dynamics, and most importantly, identify and quantify the related mechanisms leading to heat generation. This will be revealed from in-depth investigations of the switched converter under fast switching speeds and heavy load. Recognizing the key relevance of appropriate modeling tools that support this task, the second focal point of the thesis aims at developing a number of suitable models for the switching analysis of power MOSFETs. Combined with a series of design guidelines and optimization procedures, these models form the basis of a proposed methodological approach, where numerical computations replace the usually enormous experimental effort to elucidate the most effective pathways towards reducing power losses. This gives rise to the concept referred to as virtual design loop, which is successfully applied to the development of a new power MOSFET technology offering outstanding dynamic and static performance characteristics. From a system perspective, the limits of the power density conversion will be explored for this and other emerging technologies that promise to open up a new paradigm in power integration capabilities.

No description available.