As the drive continues to reduce the size of Printed Wiring Assemblies (PWAs), improve performance of electronic assemblies, and reduce costs of these products, reliable secondary (bottom) side reflow operations must be developed. Attaching Surface Mount Technology (SMT) components to the secondary side of a Printed Circuit Board (PCB) is accomplished by placing components on the PCB's secondary side and processing it through the reflow oven at this point. This board is then flipped over so that more components can be placed on the side that is facing up (primary side). The PCB must again be processed through the reflow oven. Large Integrated Circuit (IC) packages that are soldered to the secondary side fall off of the PCB during reflow of the primary side. Intuition may lead one to believe this is caused solely by weight, size, etc., but experienced personnel are not able to consistently predict which components will fail. The purpose of this work is to convey the necessary knowledge to explain and predict the behavior of components during Secondary Side Reflow (SSR). This thesis will ultimately present a method by which guidelines for SSR can be created. Currently, SSR is limited to small passive devices and small Integrated Circuit (IC) packages. It is anticipated that future PWA designs will require large ICs such as Quad Flat Packs (QFP) and Ball Grid Arrays (BGA) on the secondary side. A large variety of SMT components are available, but the focus of this research was directed towards large IC packages. Current manufacturing guidelines for such products do not exist and development of these are imperative if a costly trial and error approach is to be avoided. In an environment where product technology advancement and cost reduction are key to survival, industry must develop and understand this manufacturing process. Cost savings from SSR will be most directly realized with compressed product development cycles, reduced use of PCBs, components, and raw materials, and more efficient use of manufacturing capital and employees. These cost savings would be realized nearly immediately after a set of manufacturing guidelines is developed. / Graduation date: 2000

Graduation date: 1999

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The purpose of this research is to develop an approach to minimize makespan for assigning boards to production lines. Because of sequence-dependent setup issue, board assignment and component allocation have to be performed concurrently. An integrated methodology is proposed to obtain a solution of the two problems. The methodology consists of seven phases: PCB grouping, family decomposition, subfamily sequencing, Keep Tool Needed Soonest (KTNS), component setup determination, component allocation, and board assignment. PCB grouping based on component similarity between boards is used to reduce the problem size. Family decomposition is used when total number of feeder slots required by a family exceeds feeder capacity. Subfamily sequencing and Keep Tool Needed Soonest are applied to minimize the number of component setups. Classification of setup components into standard, semi-standard, and custom setup components is performed to reduce the complexity of the component allocation problem. A component allocation algorithm is developed to balance workload across machines. Assigning board families to production lines is performed using a modification of Longest Processing Time (LPT) rule. Assigning entire PCB families to production lines to minimize makespan is difficult to accomplish since the amount of production time for each family is very large compared to that of individual PCB lot. Splitting some subfamilies is allowed as long as this does not increase makespan. The PCB grouping, family decomposition, subfamily sequencing, Keep Tool Needed Soonest (KTNS), and component setup determination procedures are derived from published research results. The component allocation and board assignment are developed in this research, as well as an overall methodology to integrate the entire problem. Data provided by published literature are employed to evaluate performance of the component allocation algorithm and the integrated methodology. To examine the applicability of the methodology, an industrial data is used with the total imbalance due to setup time and placement time of individual PCB and global makespan as the performance measures. Experimentation is conducted with simulated data based on an industry data to investigate impact of threshold value, feeder capacity, and characteristics of data sets on system performance. / Graduation date: 2002

This research was motivated by the use of multi-track feeders in the printed circuit board (PCB) assembly. In a low volume, high mix production environment, setup time is usually considered more important than processing time. Implementation of multi-track feeders not only increases the capacity of the surface mount machines but also reduces feeder changeovers. However, improper planning could diminish these benefits. The objective of this research is to develop a process plan to minimize the feeder setups in multi-track feeder systems. Two problems have been identified: component to multi-track feeder assignment problem and PCB sequencing problem. The assignment problem is formulated as a multi-dimension symmetric assignment problem with an integer-programming model. The objective is to maximize the total similarity of the component assignment. This optimization model is implemented for small-sized problems using a commercial solver package. Due to NP-complete characteristics, heuristic algorithms are developed for solving large-scale problems and industrial cases. The Hungarian algorithm, designed for asymmetric assignment problems, is used to reduce problem size in the double feeder case. The PCB sequencing problem is solved in three stages: component and PCB grouping, intra- and inter-group PCB sequencing, and feeder setup planning. An optimal tool switch policy called Keep Tool Needed Soonest is adapted for planning the multi-track feeder setup. This research also identifies the interrelationship of the assignment problem and PCB sequencing problem. An optimal component to feeder assignment will show real advantages only when working with a well-planned PCB sequence. Data obtained from literature are used to verify the heuristic developments. The methods are also applied to industrial data for evaluation of performance of real-world problems. Experimentation is conducted with simulation data to investigate the performance of methodology for different production situations. The results show that savings of up to 85% in feeder setups can be realized with a double feeder system compared to a single feeder system, with the use of the developed methodology. The approach is also robust and efficient for different production environments. / Graduation date: 1999

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No description available.