Submitted by Caroline Xavier (caroline.xavier@pucrs.br) on 2017-09-11T13:09:26Z No. of bitstreams: 1 DIS_GUILHERME_CARDOSO_MEDEIROS_COMPLETO.pdf: 10767866 bytes, checksum: f8ce0a0593916dec149c9417c21ff36e (MD5) / Made available in DSpace on 2017-09-11T13:09:26Z (GMT). No. of bitstreams: 1 DIS_GUILHERME_CARDOSO_MEDEIROS_COMPLETO.pdf: 10767866 bytes, checksum: f8ce0a0593916dec149c9417c21ff36e (MD5) Previous issue date: 2017-08-17 / Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior - CAPES / Miniaturiza??o tem sido adotada como o principal objetivo da ind?stria de Circuitos Integrados (CIs) nos ?ltimos anos, uma vez que agrega muitos benef?cios tais como desempenho, maior densidade, e baixo consumo de energia. Junto com a miniaturiza??o da tecnologia CMOS, o aumento na quantidade de dados a serem armazenados no chip causaram a amplia??o do espa?o ocupado por mem?rias do tipo Static Random-Access Memory (SRAM) em System-on-Chips (SoCs). Tal miniaturiza??o e evolu??o da nanotecnologia proporcionou muitas revolu??es na ind?stria de semicondutores, tornando necess?rio tamb?m a melhoria no processo de fabrica??o de CIs. Devido a sensibilidade causada pela miniaturiza??o e pelas variabilidades de processo de fabrica??o, eventuais defeitos introduzidos durante fabrica??o podem danificar o CI, afetando o n?vel de confiabilidade do CI e causando perdas no rendimento por die fabricado. A miniaturiza??o adotada pela ind?stria de semicondutores impulsionou a pesquisa de novas tecnologias visando a substitui??o de transistores do tipo CMOS. Transistores FinFETs, devido a suas propriedades el?tricas superiores, emergiram como a tecnologia a ser adotada pela ind?stria. Com a fabrica??o de mem?rias utilizando a tecnologia FinFET, surge a preocupa??o com testes de mem?ria, uma vez que modelos de falhas e metodologias de teste utilizados para tecnologias planares podem n?o ser suficientes para detectarem todos os defeitos presented em tecnologias multi-gate. Uma vez que esta nova tecnologia pode ser afetada por novos tipos de falhas, testes que dependem da execu??o de opera??es, m?todos de endere?amento, checagem de padr?es, e outros tipos de condi??es de est?mulo, podem deixar de serem estrat?gias confi?veis para o teste dos mesmos. Neste contexto, este trabalho de mestrado prop?e uma metodologia baseada em hardware para testar mem?rias em FinFET que monitore par?metros do bloco de mem?ria e gere sinais baseados nessas caracter?sticas. Atrav?s do uso de sensores que monitoram os par?metros do circuito (como consumo de corrente, tens?o nas bit lines) e detectam mudan?as dos padr?es monitorados, os sensores criam pulsos que representam essas varia??es. Esses pulsos s?o modulados usando t?cnicas de modula??o. Uma vez que defeitos resistivos alteram os par?metros monitorados, c?lulas afetadas por esses defeitos apresentam diferentes sinais modulados, validando a metodologia proposta e permitindo a detec??o destes defeitos e consequentemente aumentando o yield de fabrica??o e a confiabilidade do circuito ao longo da sua vida. A metodologia baseada em hardware proposta neste trabalho foi implementada utilizando sensores integrados no pr?prio CI, e foi dividida em duas abordagens: monitoramento de consumo de corrente e monitoramento da tens?o nas bit lines. Cada abordagem foi validada com a inje??o de 12 defeitos resistivos de diferentes naturezas e localiza??es, a ap?s validados considerando diferentes temperaturas de opera??o e o impacto da varia??o de processo de fabrica??o. / Miniaturization has been the industry?s main goal over the last few years, as it brings benefits such as high performance and on-chip integration as well as power consumption reduction. Alongside the constant scale-down of Integrated Circuits (ICs) technology, the increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy great part of Systems-on-Chip (SoCs). The constant evolution of nanotechnology brought many revolutions to semiconductors, making it also necessary to improve the integrated circuit manufacturing process. Therefore, the use of new, complex processing steps, materials, and technology has become necessary. The technology-shrinking objective adopted by the semiconductor industry promoted research for technologies to replace CMOS transistors. FinFET transistors, due to their superior electrical properties, have emerged as the technology most probably to be adopted by the industry. However, one of the most critical downsides of technology scaling is related to the non-determinism of device?s electrical parameters due to process variation. Miniaturization has led to the development of new types of manufacturing defects that may affect IC reliability and cause yield loss. With the production of FinFET-based memories, there is a concern regarding embedded memory test and repair, because fault models and test algorithms used for memories based on conventional planar technology may not be sufficient to cover all possible defects in multi-gate memories. New faults that are specific to FinFETs may exist, therefore, current test solutions, which rely on operations executing specific patterns and other stressing conditions, may not stand to be reliable tools for investigating those faults. In this context, this work proposes a hardware-based methodology for testing memories implemented using FinFET technology that monitors aspects of the memory array and creates output signals deriving from the behavior of these characteristics. Sensors monitor the circuit?s parameters and upon changes from their idle values, create pulses that represent such variations. These pulses are modulated applying the pulse width modulation techniques. As resistive defects alter current consumption and bit line voltages, cells affected by resistive defects present altered modulated signals, validating the proposed methodology and allowing the detection of these defects. This further allows to increase the yield after manufacturing and circuit reliability during its lifetime. Considering how FinFET technology has evolved and the likelihood that ordinary applications will employ FinFET-based circuits in the future, the development of techniques to ensure circuit reliability has become a major concern. The presented hardware-based methodology, which was implemented using On-Chip Sensors, has been divided in two approaches: monitoring current consumption and monitoring the voltage level of bit lines. Each approach has been validated by injecting a total of 12 resistive defects, and evaluated considering different operation temperatures and the impact of process variation.