The thesis presents a qualitative survey of web services' interoperability, offering a snapshot of development and trends at the end of 2005. It starts by examining the beginnings of web services in earlier distributed computing and middleware technologies, determining the distance from these approaches evident in current web-services architectures. It establishes a working definition of web services, examining the protocols that now seek to define it and the extent to which they contribute to its most crucial feature, interoperability. The thesis then considers the REST approach to web services as being in a class of its own, concluding that this approach to interoperable distributed computing is not only the simplest but also the most interoperable. It looks briefly at interoperability issues raised by technologies in the wider arena of Service Oriented Architecture. The chapter on protocols is complemented by a chapter that validates the qualitative findings by examining web services in practice. These have been implemented by a variety of toolkits and on different platforms. Included in the study is a preliminary examination of JAX-WS, the replacement for JAX-RPC, which is still under development. Although the main language of implementation is Java, the study includes services in C# and PHP and one implementation of a client using a Firefox extension. The study concludes that different forms of web service may co-exist with earlier middleware technologies. While remaining aware that there are still pitfalls that might yet derail the movement towards greater interoperability, the conclusion sounds an optimistic note that recent cooperation between different vendors may yet result in a solution that achieves interoperability through core web-service standards.

published_or_final_version / Computer Science / Master / Master of Philosophy

Generators and goal-directed evaluation provide a rich programming paradigm when combined with traditional control structures in an imperative language. Icon is a language whose goal-directed evaluation is integrated with traditional control structures. This integration provides powerful mechanisms for formulating many complex programming operations in concise and natural ways. However, generators, goal-directed evaluation, and related control structures introduce implementation problems that do not exist for languages with only conventional expression evaluation. This dissertation presents an implementation model using recursion that serves as a basis for both an interpreter and a compiler. Furthermore, in the case of the compiler, optimizations can be performed to improve the efficiency of Icon programs, mainly by reducing the general evaluation strategy whenever possible. The dissertation describes a compile-time semantic analysis used to gather information about the properties of expressions and how they are used at their lexical sites. The optimizations that can be performed using this information are illustrated in the context of the compiler model described in the dissertation.

Photocopy of typescript. / Digitized by Kansas Correctional Industries

K.Y. Mok. / Thesis (M.Ph.)--Chinese University of Hong Kong, 1986. / Bibliography: leaf 96.

Typescript (photocopy). / Digitized by Kansas Correctional Industries

Photocopy of typescript. / Digitized by Kansas Correctional Industries

Typescript (photocopy). / Digitized by Kansas Correctional Industries

Digitized by Kansas Correctional Industries

Yu Chun-Pong. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 60-61). / Abstracts in English and Chinese. / Abstract of this thesis entitled: --- p.i / 摘要 --- p.iii / Acknowledgements --- p.iv / Table of contents --- p.v / List of Tables --- p.vi / List of Figures --- p.vii / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Asynchronous design --- p.1 / Chapter 1.2 --- Java processor for contactless smart card [3] --- p.2 / Chapter 1.3 --- Motivation --- p.3 / Chapter Chapter 2 --- Asynchronous circuit design techniques --- p.5 / Chapter 2.1 --- Overview --- p.5 / Chapter 2.2 --- Handshake protocol --- p.5 / Chapter 2.3 --- Asynchronous pipeline --- p.7 / Chapter 2.4 --- Asynchronous control elements --- p.9 / Chapter Chapter 3 --- Asynchronous Java Processor --- p.15 / Chapter 3.1 --- Instruction Set --- p.15 / Chapter 3.2 --- Architecture of the java processor --- p.17 / Chapter 3.3 --- Basic building blocks of the java processor --- p.22 / Chapter 3.4 --- Token flow --- p.32 / Chapter Chapter 4 --- Results and Discussion --- p.37 / Chapter 4.1 --- Simulation Results of test programs --- p.37 / Chapter 4.2 --- Experimental result --- p.41 / Chapter 4.3 --- Future work --- p.42 / Chapter Chapter 5 --- Conclusion --- p.45 / Appendix --- p.47 / Chip micrograph for the java processor core --- p.47 / Pin assignment of the java processor --- p.48 / Schematic of the java processor --- p.52 / Schematic of the decoder --- p.54 / Schematic of the Stage2 of the java processor --- p.55 / Schematic of the stack --- p.56 / Schematic of the block of the local variables --- p.57 / Schematic of the 16-bit self-timed adder --- p.58 / The schematic and the layout of the memory cell --- p.59 / Reference --- p.60