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Efficient reconfigurable architectures for 3D medical image compressionAfandi, Ahmad January 2010 (has links)
Recently, the more widespread use of three-dimensional (3-D) imaging modalities, such as magnetic resonance imaging (MRI), computed tomography (CT), positron emission tomography (PET), and ultrasound (US) have generated a massive amount of volumetric data. These have provided an impetus to the development of other applications, in particular telemedicine and teleradiology. In these fields, medical image compression is important since both efficient storage and transmission of data through high-bandwidth digital communication lines are of crucial importance. Despite their advantages, most 3-D medical imaging algorithms are computationally intensive with matrix transformation as the most fundamental operation involved in the transform-based methods. Therefore, there is a real need for high-performance systems, whilst keeping architectures exible to allow for quick upgradeability with real-time applications. Moreover, in order to obtain efficient solutions for large medical volumes data, an efficient implementation of these operations is of significant importance. Reconfigurable hardware, in the form of field programmable gate arrays (FPGAs) has been proposed as viable system building block in the construction of high-performance systems at an economical price. Consequently, FPGAs seem an ideal candidate to harness and exploit their inherent advantages such as massive parallelism capabilities, multimillion gate counts, and special low-power packages. The key achievements of the work presented in this thesis are summarised as follows. Two architectures for 3-D Haar wavelet transform (HWT) have been proposed based on transpose-based computation and partial reconfiguration suitable for 3-D medical imaging applications. These applications require continuous hardware servicing, and as a result dynamic partial reconfiguration (DPR) has been introduced. Comparative study for both non-partial and partial reconfiguration implementation has shown that DPR offers many advantages and leads to a compelling solution for implementing computationally intensive applications such as 3-D medical image compression. Using DPR, several large systems are mapped to small hardware resources, and the area, power consumption as well as maximum frequency are optimised and improved. Moreover, an FPGA-based architecture of the finite Radon transform (FRAT)with three design strategies has been proposed: direct implementation of pseudo-code with a sequential or pipelined description, and block random access memory (BRAM)- based method. An analysis with various medical imaging modalities has been carried out. Results obtained for image de-noising implementation using FRAT exhibits promising results in reducing Gaussian white noise in medical images. In terms of hardware implementation, promising trade-offs on maximum frequency, throughput and area are also achieved. Furthermore, a novel hardware implementation of 3-D medical image compression system with context-based adaptive variable length coding (CAVLC) has been proposed. An evaluation of the 3-D integer transform (IT) and the discrete wavelet transform (DWT) with lifting scheme (LS) for transform blocks reveal that 3-D IT demonstrates better computational complexity than the 3-D DWT, whilst the 3-D DWT with LS exhibits a lossless compression that is significantly useful for medical image compression. Additionally, an architecture of CAVLC that is capable of compressing high-definition (HD) images in real-time without any buffer between the quantiser and the entropy coder is proposed. Through a judicious parallelisation, promising results have been obtained with limited resources. In summary, this research is tackling the issues of massive 3-D medical volumes data that requires compression as well as hardware implementation to accelerate the slowest operations in the system. Results obtained also reveal a significant achievement in terms of the architecture efficiency and applications performance.
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Digitales Diktiergerät als System-on-a-Chip mit FPGA-EvaluierungsboardBretz, Daniel. January 2001 (has links)
Stuttgart, Univ., Diplomarb., 2001.
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An FPGA-based 3D backprojectorSorokin, Nikolay. Unknown Date (has links) (PDF)
University, Diss., 2003--Saarbrücken.
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Dynamically reconfigurable dataflow architecture for high performance digital signal processing on multi FPGA platformsVoigt, Sven-Ole January 2008 (has links)
Zugl.: Hamburg, Techn. Univ., Diss., 2008
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Untersuchungen zur Kostenoptimierung für Hardware-Emulatoren durch Anwendung von Methoden der partiellen LaufzeitrekonfigurationBeckert, René January 2008 (has links)
Zugl.: Chemnitz, Techn. Univ., Diss., 2008
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Evaluation of an FPGA and PCI Bus based Readout Buffer for the Atlas ExperimentMüller, Matthias. January 2005 (has links)
Mannheim, Univ., Diss., 2004.
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Der ATLAS-LVL2-Trigger mit FPGA-Prozessoren Entwicklung, Aufbau und Funktionsnachweis des hybriden FPGA/CPU-basierten Prozessorsystems ATLANTIS /Singpiel, Holger. Unknown Date (has links) (PDF)
Universiẗat, Diss., 2000--Heidelberg.
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A versatile DSP, FPGA structure optimized for rapid prototyping and digital real time simulation of power electronic and electrical drive systemsKaripidis, Claus-Ulrich. Unknown Date (has links) (PDF)
Techn. Hochsch., Diss., 2001--Aachen.
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Programmierung von FPGA-Prozessorsystemen mittels aktiver KomponentenRühl, Stephan. Unknown Date (has links) (PDF)
Universiẗat, Diss., 2001--Mannheim.
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Eine FPGA/DSP-Entwicklungsplattform für eingebettete audiosignalverarbeitende EchtzeitsystemeBeyer, Marco. Unknown Date (has links) (PDF)
Techn. Universiẗat, Diss., 2003--Berlin.
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