Thesis (M.S.)--University of Missouri-Columbia, 2004. / Typescript. Includes bibliographical references (leaf 54). Also available on the Internet.

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002. / Includes bibliographical references (leaves 111-112). Also available in electronic version. Access restricted to campus users.

Thesis (M.S.)--University of Missouri-Columbia, 2004. / Typescript. Includes bibliographical references (leaf 54). Also available on the Internet.

Direct fault testing onboard Dynamic Position Vessels is a requirement to maintain the ships classification and ensure redundancy of the power system onboard to maintain position. The most vulnerable part of the ship when testing occurs is when a three phase fault is placed on a main bus. This puts tremendous amount of strain on the system. This thesis offers an alternate and safer way to ensure the protection equipment is working properly by using a fault signal using from Programmable Logic Controller in conjunction with the protection relays. A working PSCAD model of Transocean's DEEPWATER CHAMPION was developed using a one line diagram. Using the developed PSCAD model three phase fault currents could be calculated and then simulated as a scaled down secondary current to use for testing the protection relays. To test the develop testing system different bus configurations were analyzed to determine loss of thruster capabilities which deter the vessel to maintain position. / Master of Science

Approved for public release; distribution is unlimited / The goal of this thesis is the development of a programmable logic array (PLA) that accepts multiple-valued inputs and produces multiple valued outputs. The PLA is implemented in CMOS and multiple levels are encoded as current. It is programmed by choosing transistor geometries which control the current level at which the PLA reacts to inputs. An example of a 4-valued PLA is shown. As part of this research, a C program was written that produces a PLA layout. / http://archive.org/details/designofmultiple00koyo / Major, Republic of Korea Air Force

No description available.

Emerging broadband wireless packet data networks are increasingly employing spectrally efficient modulation methods like Quadrature Amplitude Modulation (QAM) to increase the channel efficiency and maximize data throughput. Unfortunately, the performance of high level QAM modulations in the wireless channel is sensitive to channel imperfections and throughput is degraded significantly at low signal-to-noise ratios due to bit errors and packet retransmission. To obtain a more robust physical layer, broadband systems are employing multilevel QAM (M-QAM) to mitigate this reduction in throughput by adapting the QAM modulation level to maintain acceptable packet error rate (PER) performance in changing channel conditions. This thesis presents an adaptive M-QAM modem hardware architecture, suitable for use as a modem core for programmable software defined radios (SDRs) and broadband wireless applications. The modem operates in burst mode, and can reliably synchronize to different QAM constellations burst-by-burst. Two main improvements exploit commonality in the M-QAM constellations to minimize the redundant hardware required. First, the burst synchronization functions (carrier, clock, amplitude, and modulation level) operate reliably without prior knowledge of the QAM modulation level used in the burst. Second, a unique bit stuffing and shifting technique is employed which supports variable bit rate operation, while reducing the core signal processing functions to common hardware for all constellations. These features make this architecture especially attractive for implementation with Field Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs); both of which are becoming popular for highly integrated, cost-effective wireless transceivers.

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