Emerging broadband wireless packet data networks are increasingly employing spectrally efficient modulation methods like Quadrature Amplitude Modulation (QAM) to increase the channel efficiency and maximize data throughput. Unfortunately, the performance of high level QAM modulations in the wireless channel is sensitive to channel imperfections and throughput is degraded significantly at low signal-to-noise ratios due to bit errors and packet retransmission. To obtain a more robust physical layer, broadband systems are employing multilevel QAM (M-QAM) to mitigate this reduction in throughput by adapting the QAM modulation level to maintain acceptable packet error rate (PER) performance in changing channel conditions. This thesis presents an adaptive M-QAM modem hardware architecture, suitable for use as a modem core for programmable software defined radios (SDRs) and broadband wireless applications. The modem operates in burst mode, and can reliably synchronize to different QAM constellations burst-by-burst. Two main improvements exploit commonality in the M-QAM constellations to minimize the redundant hardware required. First, the burst synchronization functions (carrier, clock, amplitude, and modulation level) operate reliably without prior knowledge of the QAM modulation level used in the burst. Second, a unique bit stuffing and shifting technique is employed which supports variable bit rate operation, while reducing the core signal processing functions to common hardware for all constellations. These features make this architecture especially attractive for implementation with Field Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs); both of which are becoming popular for highly integrated, cost-effective wireless transceivers.

Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010. / Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Ghovanloo, Maysam. Part of the SMARTech Electronic Thesis and Dissertation Collection.

This master‘s final paper describes JTAG (boundary scan) interface in which discuss IEEE standart 1149.1 circuit model and the main TAP (Test Access Port) controllers instructions. Accomplished programmable integral logical ICs overview: development, leading manufacturer (ALTERA, XILINX, ACTEL) production and programmable equipment evaluation. Represented recomendation, how we can pick suitable programmable logical device. The paper presents detailed describe searching ICs family XC9500 characteristic, features and merits. In general terms presented programmable logic language VHDL value. It also produces some detailed compose describes of the project, using methods of circuit drawing and VHDL language. Master‘s hypothesis that if we will use JTAG interface processed logical programmable instrumentation in our projects we can save up time, area and improve their quality is confirmed. This is prospective technology which also soon will be in use in Lithuania.

Thesis (M.S.)--Ohio University, March, 2001. / Title from PDF t.p.

Thesis (M.S.)--Rochester Institute of Technology, 1995. / Typescript. Bibliography: leaf 55.

Thesis (M.S.)--West Virginia University, 2009. / Title from document title page. Document formatted into pages; contains xi, 102 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 77-79). WVU users: Also available in print for a fee.

Main topic of this master's thesis is proposal of automatic line for bulding and testing keys for electrical ignition of cars. In the first part of this master's thesis you can see options of layout machines and proposal of two layouts. In this part you can see all actuators and senzors with detailed description of using in application, too. Next part is about software, communication between each components and description of visualization. Last part is about recapitulate of topic and evaluation building of machines with ideas for improvement this line for future.

Avec les réductions d'échelle, les circuits électroniques deviennent de plus en plus petits, plus performants, consommant moins de puissance, mais aussi moins fiables. En effet, la fiabilité s'est récemment érigée en défi majeur dans l'industrie micro-électronique, devenant un critère de conception important, au même titre que la surface, la consommation de puissance et la vitesse. Par exemple, les défauts physiques dus aux imperfections dans le procédé de fabrication ont été observés plus fréquemment, affectant ainsi le rendement des circuits. Par ailleurs, les circuits nano-métriques deviennent pendant leur durée de vie plus vulnérables aux rayonnements ionisants, ce qui cause des fautes transitoires. Les défauts de fabrication, aussi bien que les fautes transitoires, diminuent la fiabilité des circuits intégrés. En avançant dans les nœuds technologiques, les circuits logiques programmables de type FPGA sont les premiers à entrer sur le marché, grâce à leur faible coût de développement et leur flexibilité qui leur permet d'être utilisés pour n'importe quelle application. Les FPGA possèdent des caractéristiques attrayantes, notamment pour les applications spatiales et aéronautiques, où la reconfigurabilité, les hautes performances et la faible consommation de puissance peuvent être exploitées pour développer des systèmes innovants. Néanmoins, les missions ont lieu dans un environnement rude, riche en radiations pouvant produire des erreurs soft dans les circuits électroniques. Ceci montre l'importance de la fiabilité des FPGA en tant que critère de conception dans les applications critiques. La plupart des FPGA commerciaux ont une architecture matricielle et leurs blocs logiques sont regroupés en clusters. Ainsi, cette thèse s'intéresse à la tolérance aux fautes des blocs de base ( blocs logiques élémentaires (BLE) et boîtes d'interconnexion ) dans un FPGA de type « matrice de clusters ». Dans le but d'améliorer la fiabilité de ces blocs, il est impératif de pouvoir d'abord l'évaluer, pour ensuite sélectionner la bonne technique de durcissement selon le budget mis à disposition. C'est bien le plan principal de cette thèse. Elle a essentiellement deux objectifs : (a) analyser la tolérance aux fautes des blocs de base dans un FPGA de type « matrice de clusters », et identifier les composants les plus vulnérables. (b) proposer des méthodes de durcissement à différents niveaux de granularité, en fonction du budget de durcissement. En ce qui concerne le premier objectif, une méthodologie pour évaluer la fiabilité du cluster a été proposée. Cette méthodologie emploie une méthode analytique déjà existante pour évaluer la fiabilité des circuits logiques combinatoires. La même méthode est utilisée pour identifier les blocs les plus éligibles au durcissement. Quant au deuxième objectif, des techniques de durcissement ont été proposées aux niveaux multiplexeur et transistor. Au niveau multiplexeur, deux solutions de durcissement ont été présentées. La première solution a recours à la redondance spatiale et concerne la structure du bloc logique. Une nouvelle architecture de BLE baptisée « Butterfly » est introduite. Elle a été comparée avec d'autres architectures de BLE en termes de fiabilité et de surcoût. La deuxième solution de durcissement est une technique dite « sans redondance ». Elle est basée sur une synthèse intelligente qui consiste à chercher la structure la plus fiable parmi toutes celles proposées dans la librairie du fondeur, avant d'utiliser directement de la redondance. Ensuite, au niveau transistor, de nouvelles architectures de multiplexeur, à sortie unique ou différentielles, ont été proposées. Elles ont été comparées à d'autres assemblages différents de transistors, selon des métriques de conception appropriées. / As feature sizes scale down to nano-design level, electronic devices have become smaller, more performant, less power-onsuming, but also less reliable. Indeed, reliability has arisen as a serious challenge in nowadays’ microelectronics industry and as an important design criterion, along with area, performance and power consumption. For instance, physical defects due to imperfections in the manufacturing process have been observed more frequently, impacting the yield. Besides, nanometric circuits have become more vulnerable during their lifetime to ionizing radiation which causes transient faults. Both manufacturing defects and transient faults contribute to decreasing reliability of integrated circuits. When moving to a new technology node, Field Programmable Gate Arrays (FPGAs) are the first coming into the market, thanks to their low development and Non-Recurring Engineering (NRE) costs and their flexibility to be used for any application. FPGAs have especially attractive characteristics for space and avionic applications, where reconfigurability, high performance and low-power consumption can be fruitfully used to develop innovative systems. However, missions take place in a harsh environment, rich in radiation, which can induce soft errors within electronic devices. This shows the importance of FPGA reliability as a design criterion in safety and critical applications. Most of commercial FPGAs have a mesh architecture and their logic blocks are gathered into clusters. Therefore, this thesis deals with the fault tolerance of basic blocks (clusters and switch boxes) in a mesh of clusters FPGA. These blocks are mainly made up of multiplexers. In order to improve their reliability, it is imperative to be able to assess it first, then select the proper hardening approach according to the available budget. So, this is the main outline in which this thesis is conceived. Its goals are twofold: (a) analyze the fault tolerance of the basic blocks in a mesh of clusters FPGA, and point out the most vulnerable components (b) propose hardening schemes at different granularity levels, depending on the hardening budget. As far as the first goal is concerned, a methodology to evaluate the reliability of the cluster is proposed. This methodology uses an existent analytical method for reliability computation of combinational circuits. The same method is employed to identify the worthiest components to be hardened. Regarding the second goal, hardening techniques are proposed at both multiplexer and transistor levels. At multiplexer level, two hardening solutions are presented. The first solution resorts to spacial redundancy and concerns the logic block structure. A novel Configurable Logic Block (CLB) architecture baptized Butterfly is introduced. It is compared with other hardened CLB architectures in terms of reliability and cost penalties. The second hardening solution is a redundanceless scheme. It is based on a “smart” synthesis that consists in seeking the most reliable design in a given founder library, instead of directly using a redundant solution. Then, at transistor level, new single-ended and dual-rail multiplexer architectures are proposed. They are compared to different other transistor structures, according to suitable design metrics.

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