Avec les réductions d'échelle, les circuits électroniques deviennent de plus en plus petits, plus performants, consommant moins de puissance, mais aussi moins fiables. En effet, la fiabilité s'est récemment érigée en défi majeur dans l'industrie micro-électronique, devenant un critère de conception important, au même titre que la surface, la consommation de puissance et la vitesse. Par exemple, les défauts physiques dus aux imperfections dans le procédé de fabrication ont été observés plus fréquemment, affectant ainsi le rendement des circuits. Par ailleurs, les circuits nano-métriques deviennent pendant leur durée de vie plus vulnérables aux rayonnements ionisants, ce qui cause des fautes transitoires. Les défauts de fabrication, aussi bien que les fautes transitoires, diminuent la fiabilité des circuits intégrés. En avançant dans les nœuds technologiques, les circuits logiques programmables de type FPGA sont les premiers à entrer sur le marché, grâce à leur faible coût de développement et leur flexibilité qui leur permet d'être utilisés pour n'importe quelle application. Les FPGA possèdent des caractéristiques attrayantes, notamment pour les applications spatiales et aéronautiques, où la reconfigurabilité, les hautes performances et la faible consommation de puissance peuvent être exploitées pour développer des systèmes innovants. Néanmoins, les missions ont lieu dans un environnement rude, riche en radiations pouvant produire des erreurs soft dans les circuits électroniques. Ceci montre l'importance de la fiabilité des FPGA en tant que critère de conception dans les applications critiques. La plupart des FPGA commerciaux ont une architecture matricielle et leurs blocs logiques sont regroupés en clusters. Ainsi, cette thèse s'intéresse à la tolérance aux fautes des blocs de base ( blocs logiques élémentaires (BLE) et boîtes d'interconnexion ) dans un FPGA de type « matrice de clusters ». Dans le but d'améliorer la fiabilité de ces blocs, il est impératif de pouvoir d'abord l'évaluer, pour ensuite sélectionner la bonne technique de durcissement selon le budget mis à disposition. C'est bien le plan principal de cette thèse. Elle a essentiellement deux objectifs : (a) analyser la tolérance aux fautes des blocs de base dans un FPGA de type « matrice de clusters », et identifier les composants les plus vulnérables. (b) proposer des méthodes de durcissement à différents niveaux de granularité, en fonction du budget de durcissement. En ce qui concerne le premier objectif, une méthodologie pour évaluer la fiabilité du cluster a été proposée. Cette méthodologie emploie une méthode analytique déjà existante pour évaluer la fiabilité des circuits logiques combinatoires. La même méthode est utilisée pour identifier les blocs les plus éligibles au durcissement. Quant au deuxième objectif, des techniques de durcissement ont été proposées aux niveaux multiplexeur et transistor. Au niveau multiplexeur, deux solutions de durcissement ont été présentées. La première solution a recours à la redondance spatiale et concerne la structure du bloc logique. Une nouvelle architecture de BLE baptisée « Butterfly » est introduite. Elle a été comparée avec d'autres architectures de BLE en termes de fiabilité et de surcoût. La deuxième solution de durcissement est une technique dite « sans redondance ». Elle est basée sur une synthèse intelligente qui consiste à chercher la structure la plus fiable parmi toutes celles proposées dans la librairie du fondeur, avant d'utiliser directement de la redondance. Ensuite, au niveau transistor, de nouvelles architectures de multiplexeur, à sortie unique ou différentielles, ont été proposées. Elles ont été comparées à d'autres assemblages différents de transistors, selon des métriques de conception appropriées. / As feature sizes scale down to nano-design level, electronic devices have become smaller, more performant, less power-onsuming, but also less reliable. Indeed, reliability has arisen as a serious challenge in nowadays’ microelectronics industry and as an important design criterion, along with area, performance and power consumption. For instance, physical defects due to imperfections in the manufacturing process have been observed more frequently, impacting the yield. Besides, nanometric circuits have become more vulnerable during their lifetime to ionizing radiation which causes transient faults. Both manufacturing defects and transient faults contribute to decreasing reliability of integrated circuits. When moving to a new technology node, Field Programmable Gate Arrays (FPGAs) are the first coming into the market, thanks to their low development and Non-Recurring Engineering (NRE) costs and their flexibility to be used for any application. FPGAs have especially attractive characteristics for space and avionic applications, where reconfigurability, high performance and low-power consumption can be fruitfully used to develop innovative systems. However, missions take place in a harsh environment, rich in radiation, which can induce soft errors within electronic devices. This shows the importance of FPGA reliability as a design criterion in safety and critical applications. Most of commercial FPGAs have a mesh architecture and their logic blocks are gathered into clusters. Therefore, this thesis deals with the fault tolerance of basic blocks (clusters and switch boxes) in a mesh of clusters FPGA. These blocks are mainly made up of multiplexers. In order to improve their reliability, it is imperative to be able to assess it first, then select the proper hardening approach according to the available budget. So, this is the main outline in which this thesis is conceived. Its goals are twofold: (a) analyze the fault tolerance of the basic blocks in a mesh of clusters FPGA, and point out the most vulnerable components (b) propose hardening schemes at different granularity levels, depending on the hardening budget. As far as the first goal is concerned, a methodology to evaluate the reliability of the cluster is proposed. This methodology uses an existent analytical method for reliability computation of combinational circuits. The same method is employed to identify the worthiest components to be hardened. Regarding the second goal, hardening techniques are proposed at both multiplexer and transistor levels. At multiplexer level, two hardening solutions are presented. The first solution resorts to spacial redundancy and concerns the logic block structure. A novel Configurable Logic Block (CLB) architecture baptized Butterfly is introduced. It is compared with other hardened CLB architectures in terms of reliability and cost penalties. The second hardening solution is a redundanceless scheme. It is based on a “smart” synthesis that consists in seeking the most reliable design in a given founder library, instead of directly using a redundant solution. Then, at transistor level, new single-ended and dual-rail multiplexer architectures are proposed. They are compared to different other transistor structures, according to suitable design metrics.

Approved for public release, distribution is unlimited / This thesis outlines the development, programming, and testing a logical interface between a radar system, the AN/SPS-65(V)1, and a general-purpose reconfigurable computing platform, the SRC Computer, Inc. model, the SRC-6E. To confirm the proper operation of the interface and associated subcomponents, software was developed to perform basic radar signal processing. The interface, as proven by the signal processing results, accurately reflects radar imagery generated by the radar system when compared to maps of the surrounding area. The research accomplished here will allow follow on research to evaluate the potential benefits reconfigurable computing platforms offer for radar signal processing. / Captain, United States Marine Corps

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / The Precision Fires Rocket and Missile Systems (PFRMS) Program Office continually undertakes Stockpile Reliability Testing (SRP) to ensure the validity of the accumulated weapons and increase the she lf life of these weapon systems. MLRS is a legacy weapon system that has been undergoing SRP testing for over 20 years. The PFRMS Program Office has a need for a miniature Tactical Telemetry System that will monitor the fuze performance of the MLRS Rocket during SRP testing. This paper will address a technical approach of how a small Tactical Telemetry System could be built to meet this requirement. The Tactical Telemetry system proposed in this paper will monitor fuze functions, operate across the wide environmental spectrum of the SRP tests, and physically fit in the nose area without altering the overall tactical rocket appearance or operation.

The objective of the research is to design an electro-optic control for the Active Vertical Coupler-based Optical Cross-point Switch (OXS). The electronic control should be implemented on Printed Circuit Board (PCB) and therefore the design will include the PCB design as well. The aim of the electronic control board is to process the headers of the packets prior to entering the OXS to be switched and from the information in the headers, determine the state that the OXS should be configured in. It should then configure the optical cross-point accordingly. The electronic control board should show flexibility in the sense that it can handle different types of traffic and resolve possible contention that may occur. The research seeks to understand the problems associated with Photonic Packet Switching (PPS) networks. Two of the main problems identified in a PPS network are contention resolution and the lack of variable delays for storing optical packets. The OXS was analyzed and found to meet the requirements for future ultra-high speed PPS network technology with its high extinction ratio, wide optical bandwidth, ultra-fast switching speed and low crosstalk levels. Photonic packets were generated with 4-bit, 8-bit or 16-bit headers at a bit rate of 155 Mbit/s followed by a PRBS (Pseudo Random Bit Sequence) payload at 10 Gbit/s. Different scenarios were created with these types of packets and the electro-optic control and OXS were subjected to these scenarios with the aim of testing the flexibility of the electro-optic control to control the OXS. These scenarios include: <ul><li>Fixed length packets arriving synchronously at one input of the OXS. Some packets are destined for output 1, some are destined for output 2 and some are destined for output 3, therefore realizing a 1-to-3 optical switch.</li> <li>Eight variable length packets arriving synchronously at the OXS at one input, all of them destined for one output. The electro-optic control should open the switch cell for the correct amount of time.</li> <li>Three variable length packets arriving synchronously and asynchronously at one input of the OXS. Some packets are destined for output 1 while other packets are destined for output 2. The electro-optic control should open the correct switch cell for the correct amount of time.</li> <li>Two fixed length packets arriving at the OXS synchronously on different input ports at the same time, both destined for the same output port. The electro-optic control should detect the contention and switch the packets in such a way as to resolve the contention.</li> The electro-optic control and OXS managed to switch all these types of data traffic (scenarios) successfully and resolve the contention with an optical delay buffer. The success of the results was measured in two ways. Firstly it was deemed successful if the expected output sequence was measured at the corresponding output ports. Secondly it was successful if the degradation in quality of the packet was not drastic, meaning the output packets should have an BER (Bit Error Rate) of less than 10-9. The quality of the packets was measured in the form of eye diagrams before and after the switching and then compared. The research resulted in the design and implementation of a flexible electro-optic control for the OXS. The problem of contention was resolved for fixed length synchronous packets and a proposal is discussed to store packets for variable lengths of time by using the OXS. This electro-optic control has the potential to control the OXS for traffic with higher complexities and make the OXS compatible with future developments. / Dissertation (MEng (Electronic Engineering))--University of Pretoria, 2008. / Electrical, Electronic and Computer Engineering / MEng / unrestricted

This diploma thesis treats the possibilities of the black-white picture depiction in pseudo colors (Pseudocolor). The individual methods, software or hardware are described there and the detailed block scheme of the system Pseudocolor is suggested. The block scheme is created on the basis of gained theoretical knowledge. In the thesis, individual functional blocks of the scheme are described and their circuit designs are realized. Some of the functional blocks are simulated by the PSpice program and accompanied by corresponding signal process data. The suitable choice of the active and passive components is performed, from which the general integration of the system Pseudocolor is made. All the source materials for the realization of the device are given there – double-sided drawing of the printed circuit, layout and specification of the components.