A morfologia matemática é o estudo da forma utilizando as ferramentas da teoria de conjuntos e representa uma área extremamente importante em análise de imagens. Suas operações básicas são a dilatação e a erosão, e através destas é possível realizar outras operações mais complexas. A morfologia matemática fornece ferramentas poderosas para a realização de análise de imagens em baixo nível e tem encontrado aplicações em diversas áreas, tais como: visão robótica, inspeção visual, medicina, análise de textura, entre outras. Muitas destas aplicações requerem processamento em tempo real, e para sua execução de forma eficiente freqüentemente é utilizado hardware dedicado. A análise de imagens em baixo nível geralmente envolve computações repetidas sobre estruturas grandes de dados. Assim, o paralelismo parece ser um atributo necessário de um sistema de hardware capaz de executar eficientemente estas tarefas. As ferramentas da morfologia matemática são bem adequadas à implementação em arquiteturas pipeline. A necessidade de sistemas capazes de realizar o processamento de imagens digitais em tempo real, com o menor custo e tempo de desenvolvimento, tem sido suprida pela tecnologia de dispositivos de lógica programável complexa. Assim, neste trabalho foi projetada e implementada uma arquitetura pipeline dedicada para dilatação e erosão de imagens binárias em tempo real utilizando dispositivos lógicos programáveis de alta capacidade. Esta arquitetura é capaz de processar imagens binárias de 512 x 512 pixels. Os estágios desta arquitetura são flexíveis, permitindo a reprogramação da forma e do tamanho dos elementos estruturantes utilizados nas operações morfológicas. A arquitetura desenvolvida apresentou um desempenho satisfatório, demonstrando ser uma alternativa viável e eficiente. / Mathematical morphology is a very important image analysis area that uses set theory tools to study shapes. The basic operations in mathematical morphology are dilation and erosion, these can be used for more complex operations. Mathematical morphology has powerful tools for low level image processing and has been used in a wide range of applications such as robotic vision, visual inspection, medicine and texture analysis. Low level image processing requires repetitive processing over large data structures, dedicated parallel computing hardware is often used. Complex field programmable logic devices (CPLDs) have increasingly been used for the fast development of real time image processing systems. In this work we present a pipeline architecture for real time erosion and dilation operations, the architecture was developed using high density programmable logic devices. The developed architecture can process 512 x 512 pixels binary images, and has flexible stages that can be reprogrammed according to the shape and size of the structuring elements used in the morphological operations. Tests performed using the architecture demonstrated its good performance and that it is a good and efficient alternative for dedicated morphological image processing operations.

by Lo Wing-yee. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1994. / Includes bibliographical references (leaves vii-ix). / ABSTRACT --- p.i / LIST OF TABLES --- p.iv / LIST OF FIGURES --- p.v / Chapter 1. --- INTRODUCTION --- p.1 / Chapter 1.1 --- Traditional Design Prototyping --- p.1 / Chapter 1.2 --- In-Circuit Rapid Prototyping System --- p.2 / Chapter 1.3 --- A Summary of Prototyping Systems Available --- p.5 / Chapter 1.4 --- Universal Prototyping Board (UPB) --- p.6 / Chapter 2. --- HARDWARE DESIGNS --- p.9 / Chapter 2.1 --- Bus Interconnection --- p.9 / Chapter 2.1.1 --- Fixed buses --- p.9 / Chapter 2.1.2 --- Programmable buses --- p.12 / Chapter 2.2 --- Architectural Features --- p.15 / Chapter 2.2.1 --- Field programmable gate array --- p.15 / Chapter 2.2.2 --- Microprocessor --- p.15 / Chapter 2.2.3 --- Memory --- p.16 / Chapter 2.2.4 --- Buffers --- p.18 / Chapter 3. --- SOFTWARE TOOLS --- p.20 / Chapter 3.1 --- Critical Path Analysis --- p.20 / Chapter 3.1.1 --- Algorithm of critical path analysis --- p.21 / Chapter 3.1.2 --- Computation time --- p.21 / Chapter 3.2 --- Circuit Partitioning --- p.23 / Chapter 3.2.1 --- Partitioning algorithm --- p.24 / Chapter 3.2.2 --- Effects of partitioning --- p.36 / Chapter 3.2.3 --- Partitioning parameters --- p.38 / Chapter 3.2.4 --- Pseudo-code of partitioner --- p.39 / Chapter 3.3 --- IO Assignments --- p.40 / Chapter 3.3.1 --- Connect 4 FPGAs --- p.40 / Chapter 3.3.2 --- Connect 3 FPGAs --- p.42 / Chapter 3.3.3 --- Connect 2 FPGAs --- p.44 / Chapter 3.3.4 --- System IO (Connect 1 FPGA) --- p.47 / Chapter 3.4 --- Other Tools --- p.48 / Chapter 4. --- STRUCTURE ANALYSIS --- p.49 / Chapter 5. --- RESULTS --- p.52 / Chapter 6. --- FUTURE DIRECTION --- p.73 / Chapter 6.1 --- Other Possible Configurations --- p.73 / Chapter 6.2 --- Programmable Interconnection --- p.73 / Chapter 6.3 --- Expandability of UPB --- p.74 / Chapter 7. --- CONCLUSION --- p.75 / BIBLIOGRAPHY --- p.vii / APPENDICES --- p.x

O uso de pequenos satélites tem aumentado substancialmente nos últimos anos devido ao custo reduzido de desenvolvimento e lançamento, assim como pela flexibilidade oferecida pela utilização de componentes comerciais. Este trabalho propõe o projeto e a implementação de uma plataforma para teste, controle e qualificação de circuitos integrados (Integrated Circuits, CIs) comerciais e customizados para uso em aplicações espaciais. Esta plataforma flexível pode ser ajustada a uma gama de dispositivos e interfaces, e reduz os esforços de integração desses componentes e, portanto, acelera o desenvolvimento de todo o projeto. O sistema proposto é sintetizado em um tecnologia de Arranjo de Portas Programáveis em Campo (Field Programmable Gate Array) baseado em memória Flash, que, apesar de não ser classificado para uso aeroespacial, testes demonstram a viabilidade de seu uso. Este sistema adaptável permite o controle de novas cargas-úteis e softcores para o teste e validação antes da sua aplicação em voo. A comunicação com dispositivos é feita através de protocolos préimplementados. Os resultados de testes funcionais in loco sugerem a possibilidade de aplicação desta plataforma para uso em Cubesats. A primeira aplicação desta plataforma foi no teste do controle da placa de carga-útil do NanoSatC-BR1, o primeiro nanossatélite científico brasileiro, lançado em órbita em 2014. / The number of small satellites has substantially increased in the last years due to reduced development and launching costs, as well as due to the flexibility brought by the usage of commercial off the shelf components. This work purposes the design and implementation of a platform for test, control and qualification of commercial and customized integrated circuits for space applications. This flexible platform can be adjusted to control a wide range of devices and interfaces, and is intended to reduce the integration difficulties, resulting in the speed up of some of the project stages. The platform is synthesized in a Flash-based Field Programmable Gate Array technology. The target device is not qualified for aerospace projects. Nevertheless, previous radiation tests demonstrated its hardness for space missions. The system is adaptable and makes it possible to control, test and validate new payloads and softcores before flight. The communication between devices is done through pre-implemented protocols. Functional tests suggested the possibility to apply the platform in Cubesats projects. The first application of this platform was in the NanoSatC-BR1, the first Brazilian scientific nanosatellite, to test the controller of the payload board.

The Programmable Logic Devices, PLO, have caused a major impact in logic design of digital systems in this decade. For instance, a twenty pin PLO device can replace from three hundreds to six hundreds Transistor Transistor Logic gates, which people have designed with since the 60s. Therefore, by using PLD devices, designers can squeeze more features, reduce chip counts, reduce power consumption, and enhance the reliability of the digital systems. This thesis covers the most important aspects of logic design using PLD devices. They are Logic Minimization and State Assignment. In addition, the thesis also covers a seldomly used but very useful design style, Self-Synchronized Circuits. The thesis introduces a new method to minimize Two-Level Boolean Functions using Graph Coloring Algorithms and the result is very encouraging. The raw speed of the coloring algorithms is as fast as the Espresso, the industry standard minimizer from Berkeley, and the solution is equally good. The thesis also introduces a rule-based state assignment method which gives equal or better solutions than STASH (an Intel Automatic CAD tool) by as much as twenty percent. One of the problems with Self-Synchronized circuits is that it takes many extra components to implement the circuit. The thesis shows how it can be designed using PLD devices and also suggests the idea of a Clock Chip to reduce the chip count to make the design style more attractive.

The thesis presents a new approach to the decomposition of incompletely specified functions and its application to FPGA (Field Programmable Gate Array) mapping. Five methods: Variable Partitioning, Graph Coloring, Bond Set Encoding, CLB Reusing and Local Transformation are developed in order to efficiently perform decomposition and FPGA (Lookup-Table based FPGA) mapping. 1) Variable Partitioning is a high quality hemistic method used to find the "best" partitions, avoiding the very time consuming testing of all possible decomposition charts, which is impractical when there are many input variables in the input function. 2) Graph Coloring is another high quality heuristic\ used to perform the quasi-optimum don't care assignment, making the program possible to accept incompletely specified function and perform a quasi-optimum assignment to the unspecified part of the function. 3) Bond Set Encoding algorithm is used to simplify the decomposed blocks during the process of decomposition. 4) CLB Reusing algorithm is used to reduce the number of CLBs used in the final mapped circuit. 5) Local Transformation concept is introduced to transform nondecomposable functions into decomposable ones, thus making it possible to apply decomposition method to FPGA mapping. All the above developed methods are incorporated into a program named TRADE, which performs global optimization over the input functions. While most of the existing methods recursively perform local optimization over some kinds of network-like graphs, and few of them can handle incompletely specified functions. Cube calculus is used in the TRADE program, the operations are global and very fast. A short description of the TRADE program and the evaluation of the results are provided at the_ end of the thesis. For many benchmarks the TRADE program gives better results than any program published in the literature.

Most existing computers today are built upon a subset of the arithmetic system which is based upon the foundation of set theory. All formal systems can be expressed in terms of arithmetic and logic on current arithmetic computers through an appropriate model, then work with the model using software manipulation. However, severe speed degradation is the price one must pay for using a software-based approach, making several high-level formal systems impractical. To improve the speed at which computers can implement these high-level systems, one must either design special hardware, implementing specific operations much like math and image processing coprocessors, or execute operations upon multiple processors in a parallel fashion. Due to the increase in developing applications for the manipulation of logic functions, an interest in the logic machine has arisen. Many applications such as logic optimization, simulation, pattern recognition and image processing can be better implemented with a logic machine. This thesis proposes the design, hardware realization, and testing of the iterative logic unit (ILU) of the Cube Calculus Machine II (CCM2). The CCM2 is a general purpose computer with an architecture that emphasizes a data path designed to execute operations of cube calculus, a popular algebraic model used in the minimization of Boolean functions. The ILU is an iterative logic array of cells (ITs) using internal distributed control, enabling the execution of basic cube operations, while the Control Unit (CU) handles global signals from the host computer. The ILU of the CCM2 has been realized in hardware using Xilinx Logic Cell Arrays (LCAs). FPGAs offer the logic density and versatility of gate arrays, with the off-the shelf availability and time-to-market advantages of standard user-programmable devices. These devices can be reconfigured, allowing multiple revisions and future design generations to accommodate the same device, thus saving design and production costs, an ideal solution to the resource and financial problems plaguing the University environment.

The new family of Field Programmable Gate Arrays, CLI 6000 from Concurrent Logic Inc realizes truly Cellular Logic. It has been mainly designed for the realization of data path architectures. However, the realizable logic functions provided by its macrocells and their limited connectivity call also for new general-purpose logic synthesis methods. The basic cell of CLi 6000 can be programmed to realize a two-input multiplexer ( A*B + C*B ), an AND/EXOR cell ( A*B Ea C ), or the basic 2-input AND, OR and EXOR gate. This suggests to using these cells for tree-like expansions. These "cellular logic" devices require regular connection patterns in the netlists resulting from logic synthesis. This thesis presents a synthesis tree searching program PROMPT, which generates AND/EXOR tree circuits from given Boolean functions. Such circuits have the property that the gate structures are AND/EXOR ( A *B EB C ), AND and EXOR which could be realized by the CLI6000 cells. Also, the connection. way in the circuit is that usually the output of one level gate is the input of the next level gate of the tree. This matches ideally to the architecture of the CLI6000 bussing network where the macrocells have only connections to their neighboring cells. PROMPT is based on the Davio expansions ( an equivalent of the Shannon expansions for the EXOR gates ) as its Boolean decomposition methods. The program includes three versions: exact version, heuristic version and fixed-variable version. The exact version of PROMPT generates the Permuted Reed-Muller Tree circuit which has the minimum number of gates. Such tree circuit is obtained by searching through all possible combinations of the expansion variable orders to get the one which needs the least number of gates. The heuristic version of PROMPT is designed to decrease the time complexity of the search algorithm when dealing with logic functions having many input variables. It generates a Permuted Reed-Muller Tree which may not have the minimum number of gates. However, the tree searching time in this version decreases tremendously compared to the time necessary in the exact version. The fix-variable version is developed to generate Reed-Muller Tree circuits. Such circuits will have the same expansion variables at the same tree level, so they can be easier routed after the placement to the CLI6000 chips. In short, the program PROMPT generates the PRM and RM tree circuits which are particularly well matched to both the realization of logic cell and connection structure of the CLI6000 device. Thus, the PRM and RM circuits can be easily placed and routed on the CLI6000 FPGAs.

Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 134-144). Available also in a digital version from Dissertation Abstracts.

Thesis (M.S.)--Ohio University, August, 2002. / Title from PDF t.p.

Thesis (M.S.)--Ohio University, August, 1999. / Title from PDF t.p.